Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 12/04/2023
Public
Document Table of Contents
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4.1.2.1.3. Top Congested Hierarchies and Nets Reports

If your design fails to route, you can use the Top Congested Hierarchies and Top Congested Nets reports to determine the most congested hierarchies and nets in the design. View these reports under Compilation Report > Fitter > Route Stage.

Use context menu commands to locate directly to the reported hierarchies and nets in the Text Editor, Assignment Editor, Pin Planner, Chip Planner, and other editors. Optimize your design in the reported areas to reduce the congestion and successfully route the design.

Figure 24. Example Top Congested Hierarchies Report (Truncated)


Figure 25. Example Top Congested Nets Report (Truncated)