Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 12/04/2023
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Document Table of Contents
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2.5.1. Netlist Navigator Pane

The Netlist Navigator pane displays the entire netlist in a tree format based on the hierarchical levels of the design. Each level groups similar elements into subcategories.

The Netlist Navigator pane allows you to traverse through the design hierarchy to view the logic schematic for each level. You can also select an element in the Netlist Navigator to highlight in the schematic view.

Note: The Netlist Navigator pane does not list nodes inside atom primitives.

For each module in the design hierarchy, the Netlist Navigator pane displays the applicable elements listed in the following table. Click the “+” icon to expand an element.

Table 4.  Netlist Navigator Pane Elements
Elements Description
Instances Modules or instances in the design that can be expanded to lower hierarchy levels.
Primitives

Low-level nodes that cannot be expanded to any lower hierarchy level. These primitives include:

  • Registers and gates that you can view in the RTL Viewer when using Intel® Quartus® Prime Pro Edition synthesis.
  • Logic cell atoms in the Technology Map Viewer or in the RTL Viewer when using a VQM or EDIF from third-party synthesis software

In the Technology Map Viewer, you can view the internal implementation of certain atom primitives, but you cannot traverse into a lower-level of hierarchy.

Ports

The I/O ports in the current level of hierarchy.

  • Pins are device I/O pins when viewing the top hierarchy level and are I/O ports of the design when viewing the lower-levels.
  • When a pin represents a bus or an array of pins, expand the pin entry in the list view to see individual pin names.