Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 12/04/2023
Public
Document Table of Contents
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1.4.2. Design Optimization Tools

The Intel® Quartus® Prime software provides tools help you identify design RTL and project settings that potentially limit performance.

Table 3.  Design Optimization Tools
Tool Description To Access
Design Assistant Automatically reports any violations against a standard set of Intel FPGA-recommended design guidelines, as Correct Design Assistant Rule Violations describes. Assignments > Settings > Design Assistant Rule Settings
Fast Forward Timing Closure Recommendations Fast Forward compilation generates design recommendations to help you to break performance bottlenecks and maximize use of Hyper-Registers to drive the highest performance in Intel® Stratix® 10 and Intel Agilex® 7 designs, as Implement Fast Forward Timing Closure Recommendations describes. On the Compilation Dashboard, click Fast Forward Timing Closure Recommendations.
Design Space Explorer II Provides an easy and efficient way to run seed sweeps with different combinations of design settings and constraints to identify the optimal combination for your design, as Optimize Settings with Design Space Explorer II describes. Tools > Launch Design Space Explorer II
Assignment Back-Annotation Dialog Box Back-annotation copies the last compilation's resource assignments to preserve your optimized implementation in subsequent compilations, as Back-Annotating Optimized Assignments describes. Assignments > Back-Annotate Assignments