CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/15/2022

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Document Table of Contents

1.1. CPRI Intel® FPGA IP Core Supported Features

The CPRI Intel® FPGA IP core offers the following features:

  • Compliant with the Common Public Radio Interface (CPRI) Specification v7.0 (2015-10-09) Interface Specification available on the CPRI Industry Initiative website (www.cpri.info).
  • Supports radio equipment controller (REC) and radio equipment (RE) module configurations.
  • Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, 10.1376, 12.16512 or 24.33024 Gbps) using Intel® FPGA on-chip high-speed transceivers.
  • CPRI line bit rate auto-rate negotiation support.
  • CPRI Intel® FPGA IP core variations that target an Intel® Stratix® 10 and Intel® Agilex™ device with 24.33024 Gbps line rate includes a Reed-Solomon Forward Error Correction (RS-FEC) block. This block corrects the errors on receiver side.
  • Configurable and run-time programmable synchronization mode: master port or slave port on a CPRI link.
  • Scrambling and descrambling at 8.11008, 10.1376, 12.16512 and 24.33024 Gbps.
  • Optional scrambling and descrambling at 4.9152, 6.1440, and 9.8304 Gbps.
  • Transmitter (Tx) and receiver (Rx) deterministic latency and delay measurement and calibration.
    Note: Compliant with the CPRI Specification requirements R-19, R-20, R-20A, R-21, and R-21A.
  • Optional support for single-trip delay calibration.
  • Optional round-trip delay calibration.
  • L1 link status and alarm (Z.130.0) control and status monitoring.
  • Access to all Vendor Specific data.
  • Diagnostic parallel reverse loopback paths.
  • Diagnostic serial and parallel forward loopback paths.
  • Diagnostic stand-alone slave testing mode.
  • Register access interface to external or on-chip processor, using the Intel® Avalon® Memory-Mapped (Avalon-MM) interconnect specification.
  • Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full radioframe, synchronizes the frame position with timing references, and enables routing application support from slave to master ports to implement daisy-chain topologies.
  • Optional choice of IEEE 802.3 100BASE-X compliant 10/100 Mbps MII or 1000BASE-X compliant 1Gbps GMII for Ethernet frame access.
  • Optional direct I/Q access interface enables integration of all user-defined air standard I/Q mapping schemes.
  • Optional external I/Q mapper and demapper modules with reference design support.
  • Optional external I/Q compression and decompression modules with reference design support.
  • Optional vendor specific data access interfaces provide direct access to Vendor Specific (VS), Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels.
  • Optional HDLC serial interface provides direct access to slow control and management subchannels.
  • Optional L1 inband interface provides direct access to Z.130.0 link status and alarm control word.