CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/15/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.6. Simulating Intel FPGA IP Cores

The Intel® Quartus® Prime software supports RTL- and gate-level design simulation of Intel FPGA IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The IP generation output also includes scripts to compile and run basic testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.