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- 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
If you turn on Enable all control word access via management interface in the CPRI parameter editor, you can access all CPRI hyperframe control words through this interface.
The control and status interface is an Avalon-MM slave interface. Depending on the value you specify for Avalon-MM interface addressing type in the CPRI parameter editor, the interface implements word addressing or byte addressing. If you specify word addressing, you must connect other design components correctly to the interface to ensure the Avalon-MM byte addresses appear on the CPRI IP CPU interface as word addresses.
An on-chip processor such as the Nios II processor, or an external processor, can access the CPRI configuration address space using this Avalon-MM interface.
CPU Interface Signals
Accessing the Hyperframe Control Words
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