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- 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface
3.14.2. Ethernet PCS Bypass Mode
Due to market needs, the Ethernet PCS bypass mode feature has been added to this IP. If you set the value of the Ethernet PCS interface parameter to GMII and you selected Bypass Ethernet PCS in the CPRI parameter editor, your IP core includes this alternate GMII interface.
By selecting this feature, the internal Ethernet PCS block is entirely bypassed. A 10-bit data interface is exposed which connects to an internal FIFO on both transmit and receive side respectively. You must use your own Ethernet PCS block and present the data to or receive the data from this 10-bit interface.
An example of this feature is to use your own custom Ethernet PCS block with 4B/5B encoding for GMII instead of the standard 8B/10B encoding. In this example, you must use two parallel 4B/5B encoders to communicate with the 10-bit interface.
|gmii_rxclk||Input||Clocks the GMII receiver interface. You must drive this clock at the frequency of 125 MHz.|
|gmii_rxreset_n||Input||Resets the GMII receiver interface and FIFO read logic. This reset signal is active low.|
|gmii_rx_fifo_rdata||Output||10-bit data output from the internal FIFO. An example usage: connect this port to input of two 5B/4B decoder or one 10B/8B decoder.|
|gmii_rx_fifo_rvalid||Output||Indicates that the internal FIFO is filled with Ethernet data received through CPRI link. You are expected to align the data before feeding to the decoder(s).|
|gmii_txclk||Input||Clocks the GMII transmitter interface. You must drive this clock at the frequency of 125 MHz.|
|gmii_txreset_n||Input||Resets the GMII transmitter interface and FIFO write logic. This reset signal is active low.|
|gmii_txfifo_status||Output||Ethernet TX PCS FIFO fill level status. The value indicates:
|gmii_tx_fifo_wdata||Input||10-bit data input that is connected to the internal FIFO. An example usage: connect this port to output of two 4B/5B encoders or one 8B/10B encoder.|
|gmii_tx_fifo_wready||Output||Indicates that the internal FIFO is ready to take data, you may send data on the next clock cycle. The purpose of the internal FIFO is for clock domain crossing between Ethernet clock domain and CPRI core clock domain. You are expected to buffer the data as necessary before inserting through gmii_tx_fifo_wdata port.|
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