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- 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface
2.5.1. Adding the Transceiver TX PLL IP Core
The CPRI Intel® FPGA IP core requires that you generate and connect a TX transceiver PLL IP core for V-series, Intel® Arria® 10, and Intel® Stratix® 10 L- and H-tile device variations. The transceiver PLL IP core configures the TX PLL in the transceiver on the device, but you must generate the transceiver PLL IP core separately from the CPRI IP core in the Intel® Quartus® Prime software. If you do not generate and connect the transceiver PLL IP core, the CPRI IP core does not compile.
In the Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile device variations, the PHY includes a transceiver TX PLL and you do not need to instantiate and connect a TX transceiver PLL IP core.
You can use the IP Catalog to generate the external PLL IP core that configures a TX PLL on the device. In the IP Catalog, select an IP core that configures an appropriate PLL on your target device.
For your Stratix V, Arria V, and Cyclone V designs, you can select Intel FPGA PLL (FPLL) or Transceiver PLL in the IP Catalog. In the parameter editor for the TX PLL IP core you select, you must set the PLL output frequency to the expected input frequency for the CPRI IP core xcvr_ext_pll_clk input signal.
For your Intel® Arria® 10 design, you can select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, or Arria 10 FPLL in the IP Catalog.
For your Intel® Stratix® 10 L- and H-tile designs, you can select L-Tile/H-Tile Transceiver ATX PLL Intel Stratix 10 FPGA IP, L-Tile/H-Tile Transceiver CMU PLL Intel Stratix 10 FPGA IP, or L-Tile/H-Tile fPLL Intel Stratix 10 FPGA IP in the IP Catalog.
In the parameter editor for the TX PLL IP core you select, you must set the following parameter values:
- Set the PLL output frequency to one half the per-lane data rate of the IP core variation, multiplied by the value of the Transmitter local clock division factor parameter of the CPRI IP core.
For example, if your CPRI IP variation has a CPRI line bit rate of 10.1376 Gbps and you set the Transmitter local clock division factor to the value of 1, you must set the TX PLL PLL output frequency parameter to the value of 5068.8 MHz.
- Set the PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter.
For example, if your CPRI IP variation has a CPRI line bit rate of 10.1376 Gbps and you set the Transmitter local clock division factor parameter to the value of 1, you can set the PLL reference clock frequency to the value of 307.2 MHz.
You must connect the external TX PLL signals and the CPRI IP core transceiver TX PLL interface signals according to the following rules.
|CPRI IP Signal||TX PLL Type||Device||TX PLL Signal|
|xcvr_ext_pll_clk (input)||CMU and ATX PLL||Intel® Arria® 10 and Intel® Stratix® 10||tx_serial_clk|
|fPLL||Intel® Arria® 10 and Intel® Stratix® 10||tx_serial_clk|
If your CPRI IP core is an RE slave, drive the input signal of the external PLL IP core with the output of the off-chip cleanup PLL.
User logic must provide the connections. Refer to the Figure 1 to see how to connect the external TX PLL to a single CPRI IP core.
- Select the E-Tile Transceiver Native PHY
- In the parameter editor, set the following parameter values:
- Set the Transceiver configuration rules to PLL
- Set the SerDes/Output Driver Enable Mode to Disable output drivers
- Set the PLL output clock frequency to 805.6640625 MHz
- Set the PLL reference clock frequency to 156.250000 MHz
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