CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/15/2022
Public

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Document Table of Contents

3.1. Interfaces Overview

Figure 11.  CPRI Intel® FPGA IP Core InterfacesThe IP core assembles the outbound CPRI frame control words and data from all of these interfaces, and unloads and routes control words and data from the inbound CPRI frame to the appropriate interfaces, based on configuration and register settings. With parameter settings, you control the presence or absence of the AUX interface, the L1 control and status interface, and each of the interfaces that provide dedicated access to specific parts of the CPRI frame. In contrast, the CPRI interface, the transceiver interfaces, and the software interface to the IP core registers are always implemented.


Multiple interfaces control the contents of the outbound CPRI frame control words and data. The CPRI implements the following transmission priorities among these interfaces:

  • CPRI frame control words:
    1. If the IP core implements the AUX interface, the AUX interface aux_tx_data bus, with appropriate delay, has first priority in filling in the outbound CPRI frame control words.
    2. If the IP core does not implement the AUX interface, or the aux_tx_mask value associated with the relevant incoming data blocks the relevant aux_tx_data bits, each of the following interfaces, if implemented, has secondary priority in filling the relevant part of the outbound CPRI frame control words:
      • Real-time vendor specific interface (RTVS)
      • Vendor specific interface (VS)
      • AxC control information interface (Ctrl_AxC)
    3. For any part of the CPRI frame control words not filled in by one of the previous methods, the transmission-enabled values most recently written to the control transmit table through the full control word access registers CTRL_INDEX and TX_CTRL determine the contents of the outbound CPRI frame control words. If the most recently written word for a CPRI frame position is not transmission-enabled, no transmission is authorized from the control transmit table to that CPRI frame position.
    4. If none of the previous methods provides the content for a position in the CPRI frame control word, the following interfaces, if implemented, have the lowest priority in filling the relevant part of the outbound CPRI frame control words:
      • Fast control and management (Ethernet) MII or GMII interface
      • Slow control and management (HDLC) serial interface
      • L1 control and status interface
      • Dedicated registers that contain or control content for control word positions in the CPRI frame. For example, the rx_prot_ver_filter field of the PROT_VER register
      • Transmission of special symbols according to the CPRI protocol. For example, K28.5, D16.2, /S/, or /T/
  • CPRI frame I/Q data words:
    1. If the IP core implements the AUX interface, the AUX interface aux_tx_data bus, with appropriate delay, has first priority in filling in the outbound CPRI frame I/Q data words.
    2. If the IP core does not implement the AUX interface, or the aux_tx_mask value associated with the relevant incoming data blocks the relevant aux_tx_data bits, the Direct I/Q interface, if implemented, has secondary priority in filling the relevant part of the outbound CPRI frame I/Q data words.

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