Visible to Intel only — GUID: nik1411442186534
Ixiasoft
Visible to Intel only — GUID: nik1411442186534
Ixiasoft
3.19.7. Interface to the External PLL
Signal Name |
Direction |
Description |
---|---|---|
xcvr_ext_pll_clk | Input | Clocks the transmitter PMA. You should drive this input clock with the output of the external transceiver TX PLL. In Arria 10 devices, you have a choice of different TX PLL IP cores to configure. You must ensure that you configure a PLL IP core that is capable of driving the frequency that the CPRI IP core requires to run at the specified CPRI line bit rate. |
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