AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022

Intel® Arria® 10 Power Reduction Techniques

Intel® Arria® 10 devices implement several power reduction techniques.
Table 1.  Strategies for Reducing Power Consumption
Power Reduction Technique Description
Low Static Power Device Grades Provides flexibility to Intel devices that have been tested for static power. These devices have the –L suffix.
Programmable Power Technology Enables lower power transistors for non-performance-critical paths to reduce static power. This is achieved during compilation of the FPGA design in Intel® Quartus® Prime.
SmartVID Enables the device to run at lower than default VCC while retaining the similar performance level of the specific device speed grade, reducing static and dynamic power. This requires devices screened for proper operation. These devices have the —V suffix.