AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022

PMBus SmartVID

In PMBus SmartVID, the VRM is initially set to output a default voltage (0.9 V) required by the FPGA device at power-on. Once the FPGA device is successfully powered-on and configured, the FPGA uses PMBus to inform the VRM that a voltage change is requested. Based on the new configuration, the VRM re-adjusts (raises or lowers) its output voltage automatically to meet the new voltage required by the FPGA. In turn, the Intel® Arria® 10 device’s VCC core power can be reduced by the square of the voltage multiplied by the current.

Implementing this feature requires both hardware and software (IP) support. For the hardware portion, the selected VRM for the VCC core must support the PMBus interface and remote sensing.

Figure 16. PMBus SmartVID Block DiagramThis PMBus SmartVID implementation uses the a Digital PowerSoC with PMBus Interface to deliver VCC core current.