AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022
Public

Power Reduction and Performance

The Intel® Arria® 10 family operates at higher performance levels than prior generation 28-nm FPGAs. With 20-nm design rules, you can achieve significant power savings compared to 28-nm FPGAs. You can achieve even more power savings by applying additional power reduction techniques on the core voltage.

Figure 1. Power Consumption ComparisonPotential reduction in power compared to the lowest-power mid-range 28-nm generation FPGAs.

Smaller geometries and changes to the basic architecture provide the initial power savings of up to 15% over prior generation Arria® V devices. Any static power increases are offset by reductions in dynamic power for an overall total power reduction. You can achieve up to 40% additional power savings through static power binning, and by controlling the core voltage. You can control the core voltage through SmartVID.