AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022

Parallel VID

In parallel VID, the VRM is initially set to output a default voltage required by the FPGA device at power-on. Once the FPGA device is successfully powered on and configured, the FPGA outputs an 7-bit VID code (VID[6:0]) to the VRM. In a system using a VRM that uses 8 bits, the LSB is grounded. This informs the VRM that a voltage change is requested. Based on this unique code, the VRM re-adjusts (raises or lowers) its output voltage automatically to meet the new voltage required by the FPGA. This reduces the VCC core power by the square of the voltage multiplied by the current.

An implementation of this feature requires both hardware and software (IP) support. For the hardware portion, the selected VRM for the VCC core must support a parallel VID interface capable of supporting the VID voltage levels required by the Intel® Arria® 10 FPGA. Additionally, because the VCC core can sink over 100 A of current, you must account for the DC IR drop of the PCB VCC plane and device package. This compensation requires the VRM to support remote sensing.

Figure 14. Parallel VID Block DiagramParallel VID implementation using a parallel VID controller + 4x powertrain solution delivering up to 160 A (40 A per phase) of VCC core current demanded by high-end FPGA applications.
Figure 15. VID READY Generation