AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

Single-Wire Interface PWM System Implementation

The single-wire interface is scheduled for release with Intel® Quartus® Prime software version 16.0. Please contact your sales representative for availability of single-wire interface support ahead of Intel® Quartus® Prime software version 16.0.

Figure 11. Single-Wire Interface PWM System Implementation Example

PWM VID feature has the following implementation requirements:

  • General purpose I/O (GPIO) VDD must be held to 1.8 V+/-1% (tighter than pin connection guideline requirements).
  • Slew rates of GPIO edges must be held to < 2 ns.
  • GPIO output driver configuration must be push-pull with Rds < 25 Ω for both p-channel field effect transistor (pFET) and negative channel field effect transistor (nFET), such as 1.8 V SSTL Class II driver.
  • Resistor insertion network must be scaled for suitable insertion values for the 10 mV/LSB VID steps.
  • Resistor insertion network impedance must be high enough that 25-Ω driver resistance results in < 1% voltage error (about 30 kΩ).
  • Slew rate of the VID changes must be limited to a maximum of 10 mV/20 µs by the regulator settings or the time constant of the resistor VID insertion network.
  • The sense line current of the regulator(s) must not cause a voltage setting error of more than 1 mV with the VID resistor insertion network.
  • An external reference for the voltage ADC must be used which has an accuracy over all causes of ±0.2% as shown in Figure 10.
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