AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022

Parallel SmartVID Regulator Implementation Guidelines

Parallel SmartVID regulator implementation with Intel® Arria® 10 devices requires the following characteristics:
  • The boot voltage must be in default value (0.9 V) before VID is applied.
  • The regulator must accept parallel VID logic signals with a maximum logic voltage of 1.8 V. If you need a higher voltage for the signals to the regulator, then a level shifter may be inserted between the FPGA and the regulator if necessary.
  • The 8-bit parallel VID code must be similar to the lowest 6 bits of the Intel VRM 11 8-bit VID code. The exception is that the voltage least significant bit (LSB) step size is 5 mV instead of 6.25 mV. The range of adjustment must include 0.83 V to 0.95 V. The Parallel VID code only uses even codes (10 mV steps); thus the LSB can be omitted. The VID code will change by no more than 10 mV per step. See Parellel VID.
  • The regulator must accept a VID update rate of 10 ms. Additionally, the voltage must reach within the tolerance envelope (±5 mV of the new VID value) within 10 ms of the last transition on the VID signals.
  • If you require multiple parallel regulators to achieve the output current target, then the group of regulators must behave in the same way as a single regulator with respect to the VID functions.
  • The regulator(s) must meet the static and ripple (±30 mV) and dynamic (±5%) power tolerances during all phases of power delivery after the boot voltage is reached. Refer to the specifications described in the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines.