AN 711: Power Reduction Features in Intel® Arria® 10 Devices

ID 683566
Date 5/27/2022
Public

Parallel Control System

Note: Currently, the parallel control system is being implemented on some Intel® FPGA development boards. Contact your sales and service representative for availability.
Figure 4. Parallel Control System

The parallel output configuration uses an on-FPGA VID soft controller and parallel voltage regulator controller system. Together they create a value necessary to drive the correct data to the voltage regulator. The regulator decodes the parallel data and adjusts the voltage level to the FPGA. At power up, the bias network,which consists of weak pull-up and pull-down resistors, establishes the code for the default VCC voltage for the FPGA. When the SmartVID Controller IP takes control and is done with initializations, it outputs the voltage code. It then enables the tri-state buffer, taking control of the VCC level. Intel recommends that the enable signal originate from a specific pin (RZQ_2A) on the FPGA. Refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines for more information about pin assignments.