Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

9.2.1.3.2. Using the HAL Interrupt API with the VIC

The Intel FPGA driver for the VIC component supports the HAL enhanced interrupt API.

The VIC driver provides support for multiple, daisy­chained VIC devices. It also includes support for shadow register sets. A BSP driver setting allows you to enable automatic pre-emption (fast nested interrupts). Automatic pre-emption means that the Nios® II processor leaves maskable exceptions enabled when accepting a hardware interrupt.

For more information about fast nested interrupts, refer to “Exception Processing” in the "Programming Model" chapter of the Nios II Processor Reference Handbook.

The VIC device driver also provides the following device-specific functions:

  • int alt_vic_sw_interrupt_set(alt_u32 ic_id, alt_u32 irq);
  • int alt_vic_sw_interrupt_clear(alt_u32 ic_id, alt_u32 irq);
  • alt_u32 alt_vic_sw_interrupt_status(alt_u32 ic_id, alt_u32 irq);
  • int alt_vic_irq_set_level(alt_u32 ic_id, alt_u32 irq, alt_u32 level);

    For more information, refer to a detailed discussion of the VIC device-specific driver routinesin the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.

The EIC driver controls where hardware interrupt vector tables are located. For example, the Intel FPGA VIC driver locates the vector table in the .text section by default, but allows you to position the vector table in a different section with a driver setting.

Note: The memory in which you place the vector table must be connected to both instruction and data master ports on the Nios® II processor.