Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

9.1.2.2.3. Requested Register Set

If shadow register sets are implemented on the Nios® II core, an EIC specifies a requested register set (RRS) when it asserts an interrupt request. When the Nios® II processor takes the hardware interrupt, the processor switches to the requested register set. When an interrupt has a dedicated register set, the ISR avoids the overhead of saving registers for a context switch.

Multiple hardware interrupts can be configured to share a register set. However, at run time, the Nios® II processor does not allow pre-emption between interrupts assigned to the same register set unless this feature is specifically enabled. In this case, the ISRs must be written so as to avoid register corruption.

For more information, refer to an example of a driver that manages pre-emption within a register set in the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.