Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

9.1.3.4. How an External Interrupt Controller Works

With an EIC, the Nios® II processor supports an arbitrary number of independent hardware interrupt signals. Interrupts are typically vectored, with interrupt priority levels associated in hardware. Vectoring allows the Nios® II processor to transfer control directly to each ISR. Hardware interrupt levels allow the most critical interrupts to pre-empt lower-priority interrupts. Because both of these features are implemented in hardware, the system can handle an interrupt without executing general exception funnel code.

Note: The details of hardware interrupt vectoring and prioritization are specific to the EIC implementation.

For more information, refer to an example of an EIC implementation in the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.

Note: The HAL supports external interrupt controllers only if they are connected in one of the following ways:
  • Directly to the Nios® II EIC interface
  • Through the daisy-chain port on another EIC