Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

10.6. Managing Cache in Multi-Master and Multi-Processor Systems

The Nios® II architecture does not provide hardware cache coherency. Instead, software cache coherency must be provided when communicating through shared memory. The data cache contents of all processors accessing the shared memory must be managed by software to ensure that all masters read the most recent values and do not overwrite new data with stale data. This management is done by using the data cache flushing and bypassing facilities to move data between the shared memory and the data cache(s) as needed.

Uncached data and cached data can no longer be allocated on the same line in the data cache because the Nios® II core does not update the cache in an uncached line. This is the behavior for Nios® II Classic. If you have existing Nios® II code and use a Nios® II/f with a data cache, then you have to check your software to ensure that it does not mix cacheable and uncacheable data on the same cache line.

Nios® II provides two options for data cache bypass:
  • Bit-31cache bypass is set by default for compatibility
  • If 32-bit addressing is selected, then any code/drivers that rely on bit-31 cache bypass needs modification to use cache bypass macros/instructions or the peripheral memory region.