Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

9.1.2.2. External Interrupt Concepts

The EIC interface enables the Nios® II processor to work with a separate external interrupt controller component. An EIC can be a custom component that you provide. Intel FPGA provides an example of an EIC, the vectored interrupt controller (VIC).

For more information about the VIC, refer to the "Vectored Interrupt Controller Core" chapter in the Embedded Peripherals IP User Guide.

With an EIC, hardware interrupts are handled separately from software exceptions. Hardware interrupts have separate vectors and funnels. Each interrupt can have its own handler, or handlers can be shared. Software exception handling is the same as with the IIC.

The EIC interface provides extensive capabilities for customizing your interrupt hardware. You can design, connect and configure an interrupt controller that is optimal for your application.

When an external hardware interrupt occurs, the Nios® II processor transfers control to an individual vector address, which can be unique for each interrupt. The HAL provides the following services:

  • Registering ISRs
  • Setting up the vector table
  • Transferring control from the vector table to your ISR

An EIC can be used with shadow register sets. A shadow register set is a complete alternate set of Nios® II general-purpose registers, which can be used to maintain a separate runtime context for an ISR.

An EIC provides the following information about each hardware interrupt: