Nios® II Software Developer Handbook

ID 683525
Date 8/28/2023
Public
Document Table of Contents

9.5.3.1. Interrupt Funnel for the Internal Interrupt Controller

With the IIC, the Nios® II processor supports 32 hardware interrupts. In the HAL funnel, hardware interrupt 0 has the highest priority, and 31 the lowest. This prioritization is a feature of the HAL funnel, and is not inherent in the Nios® II interrupt controller.

The hardware interrupt funnel calls the user-registered ISRs. It goes through the IRQs in ipending starting at 0, and finds the first (highest priority) active IRQ. Then it calls the corresponding registered ISR. After this ISR executes, the funnel begins scanning the IRQs again, starting at IRQ0. In this way, higher-priority interrupts are always processed before lower-priority interrupts. When all IRQs are clear, the hardware interrupt funnel returns to the top level.

When the interrupt vector custom instruction is present in the Nios® II processor, the HAL source detects it at compile time and generates code using the custom instruction.

For more information, refer to the “Using the Interrupt Vector Custom Instruction” chapter.