Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

Download PDF
ID 683512
Date 12/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Data Plane Development Kit Overview 3. IFPGA Base Code Design 4. Ethernet Group and Retimer API 5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000
1. About this Document x
1.1. About this Document 1.2. Acronym List
2. Data Plane Development Kit Overview x
2.1. DPDK Intel® FPGA PAC N3000 Software Overview 2.2. DPDK Intel® FPGA PAC N3000 Software Components 2.3. FPGA Scan and Enumeration 2.4. OPAE User Mode Driver 2.5. OPAE User Mode Driver API Summary
2.4. OPAE User Mode Driver x
2.4.1. OPAE FPGA Adapter 2.4.2. OPAE Manager 2.4.3. OPAE Accelerator 2.4.4. OPAE Bridge
2.4.1. OPAE FPGA Adapter x
2.4.1.1. opae_adapter_init() 2.4.1.2. opae_adapter_data_alloc() 2.4.1.3. opae_adapter_enumerate() 2.4.1.4. opae_adapter_destroy()
2.4.2. OPAE Manager x
2.4.2.1. opae_manager_alloc() 2.4.2.2. opae_manager_flash() 2.4.2.3. opae_manager_get_eth_group_region_info() 2.4.2.4. Sensor Information 2.4.2.5. opae_mgr_get_sensor_value_by_name() 2.4.2.6. opae_mgr_get_sensor_value_by_id() 2.4.2.7. opae_mgr_get_sensor_value() 2.4.2.8. opae_manager_networking_ops
2.4.3. OPAE Accelerator x
2.4.3.1. opae_accelerator_alloc() 2.4.3.2. opae_acc_get_uuid() 2.4.3.3. opae_acc_get_region_info() 2.4.3.4. opae_acc_get_info()
2.4.4. OPAE Bridge x
2.4.4.1. opae_bridge_alloc() 2.4.4.2. opae_bridge_reset()
2.5. OPAE User Mode Driver API Summary x
2.5.1. Example Code
3. IFPGA Base Code Design x
3.1. FPGA Management 3.2. Accelerator Access and Control
4. Ethernet Group and Retimer API x
4.1. opae_manager_get_eth_group_nums() 4.2. opae_manager_get_eth_group_info() 4.3. opae_manager_eth_group_write_reg() 4.4. opae_manager_eth_group_read_reg() 4.5. opae_manager_get_eth_group_region_info() 4.6. Data Structures for Retiming 4.7. opae_manager_get_retimer_info() 4.8. opae_manager_get_retimer_status()
1. About this Document
2. Data Plane Development Kit Overview
3. IFPGA Base Code Design
4. Ethernet Group and Retimer API
5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000

2.4.2.4. Sensor Information

The Intel® MAX® 10 Board Management Controller monitors approximately 19 sensors. The OPAE Manager enumerates all the sensors and adds the sensors to a global list. The FPGA reads this information through its SPI interface.

The following data structure describes the sensor info: 

struct opae_sensor_info {
        TAILQ_ENTRY(opae_sensor_info) node;
        const char *name;
        const char *type;
        unsigned int id;
        unsigned int high_fatal;
        unsigned int high_warn;
        unsigned int low_fatal;
        unsigned int low_warn;
        unsigned int hysteresis;
        unsigned int multiplier;
        unsigned int flags;
        unsigned int value;
        unsigned int value_reg;
};
Table 4.  opae_sensor_info Fields
Data Structure Field Name Description
name A pointer to the name of the sensor.
type The sensor type, such as temperature sensor or voltage sensor.
id The Intel® FPGA PAC N3000 hardware ID for this sensor.
high_fatal Specifies a fatal threshold for a sensor.
high_warn Specifies a warning threshold for a sensor.
low_fatal Specifies the low fatal threshold for a sensor.
low_warn Specifies the low warning threshold for a sensor.
hysteresis Specifies the hysteresis of a sensor.
multiplier Specifies the multiplier for a sensor.
flags Specifies sensor flags.
value Specifies sensor data.
value_reg Specifies the sensor register in the Intel® MAX® 10 device.
Level Two Title