Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

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ID 683512
Date 12/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Data Plane Development Kit Overview 3. IFPGA Base Code Design 4. Ethernet Group and Retimer API 5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000
1. About this Document x
1.1. About this Document 1.2. Acronym List
2. Data Plane Development Kit Overview x
2.1. DPDK Intel® FPGA PAC N3000 Software Overview 2.2. DPDK Intel® FPGA PAC N3000 Software Components 2.3. FPGA Scan and Enumeration 2.4. OPAE User Mode Driver 2.5. OPAE User Mode Driver API Summary
2.4. OPAE User Mode Driver x
2.4.1. OPAE FPGA Adapter 2.4.2. OPAE Manager 2.4.3. OPAE Accelerator 2.4.4. OPAE Bridge
2.4.1. OPAE FPGA Adapter x
2.4.1.1. opae_adapter_init() 2.4.1.2. opae_adapter_data_alloc() 2.4.1.3. opae_adapter_enumerate() 2.4.1.4. opae_adapter_destroy()
2.4.2. OPAE Manager x
2.4.2.1. opae_manager_alloc() 2.4.2.2. opae_manager_flash() 2.4.2.3. opae_manager_get_eth_group_region_info() 2.4.2.4. Sensor Information 2.4.2.5. opae_mgr_get_sensor_value_by_name() 2.4.2.6. opae_mgr_get_sensor_value_by_id() 2.4.2.7. opae_mgr_get_sensor_value() 2.4.2.8. opae_manager_networking_ops
2.4.3. OPAE Accelerator x
2.4.3.1. opae_accelerator_alloc() 2.4.3.2. opae_acc_get_uuid() 2.4.3.3. opae_acc_get_region_info() 2.4.3.4. opae_acc_get_info()
2.4.4. OPAE Bridge x
2.4.4.1. opae_bridge_alloc() 2.4.4.2. opae_bridge_reset()
2.5. OPAE User Mode Driver API Summary x
2.5.1. Example Code
3. IFPGA Base Code Design x
3.1. FPGA Management 3.2. Accelerator Access and Control
4. Ethernet Group and Retimer API x
4.1. opae_manager_get_eth_group_nums() 4.2. opae_manager_get_eth_group_info() 4.3. opae_manager_eth_group_write_reg() 4.4. opae_manager_eth_group_read_reg() 4.5. opae_manager_get_eth_group_region_info() 4.6. Data Structures for Retiming 4.7. opae_manager_get_retimer_info() 4.8. opae_manager_get_retimer_status()
1. About this Document
2. Data Plane Development Kit Overview
3. IFPGA Base Code Design
4. Ethernet Group and Retimer API
5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000

2.1. DPDK Intel® FPGA PAC N3000 Software Overview

The DPDK Intel® FPGA PAC N3000 includes the following components:

  • The Poll Mode Driver (IPN3KE) is a user-mode driver for the Intel Ethernet Controller XL710 and Intel® Arria® 10 FPGA. This driver implements the rte_ethdev API. This Poll Mode Driver works with the Intel-provided FPGA factory image.
  • The FPGA Device Driver (IFPGA Rawdev) binds to the Intel® Arria® 10 FPGA on the Intel® FPGA PAC N3000. The IFPGA driver calls API functions that the Open Programmable Acceleration Engine (OPAE) User Mode Driver (UMD) exports to enumerate and discover the features of the FPGA and Accelerator Functional Unit (AFU). In addition, the IFPGA_Rawdev driver works in coordination with the Open Programmable Acceleration Engine (OPAE) share code to provide the following common FPGA management functions:
    • AFU identification
    • Thermal management
    • Retimer link status and statistics
  • The Intel® FPGA PAC N3000 supports the following Ethernet configurations:
    • 8x10 (4 lanes in each quad small form factor pluggable (QSFP), 40 (GbE))
    • 2x2x25 (2 lanes in each QSFP, 25 GbE)
    • 4x25 (4 lanes in one of the QSFP, 25 GbE)
  • The OPAE UMD provides interfaces for user space applications to configure, enumerate, open, and access Intel FPGA AFUs.
  • The IFPGA bus provides a mechanism for AFU devices to register on the bus. The IFPGA bus logic compares the AFU universal unique identifier (UUID) to the UUIDs of registered AFU drivers. If a driver matches the AFU UUID, the AFU driver probe routine runs. The AFU driver for the default Intel-provided factory image loaded on the FPGA is IPN3KE PMD.
Figure 1. DPDK IFPGA Bus Scan

When the DPDK application runs, this application performs two scans:

  • PCIe* scan—A kernel module, such as vfio-pci driver, performs this scan. This scan is a legacy DPDK PCIe* device scan which discovers the Intel® Arria® 10 FPGA as a PCIe* device. This scan uses the /sys kernel interface to read the address space and map to the application space.
  • AFU scan—This scan adds the AFU discovered to IFPGA bus. The ifpga bus scans the AFU device, identifies and then calls the corresponding AFU driver probe routine.
Figure 2. DPDK Line Side and Host Side Status Representation

The MACs inside the Intel® Arria® 10 FPGA connect to both line side and host side Ethernet ports. The line side port performs retiming and connects to the Ethernet network backbone. The host side port is the Intel Ethernet Controller XL710. DPDK software provides line side statistics and link status from the IPN3KE driver and gets the host side statistics from the XL710 Ethernet controller. The Ii40e PMD identifies the available XL710 ports and provides statistics by reading the XL710 MAC. The IPN3KE PMD probes the corresponding line side ports to get link status and statistics. The IPN3KE PMD probes the line side ports as port representors.

For a general overview of port-representors refer to Port Representors in Data Plane Development Kit 18.05.1 Release.

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