Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

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ID 683512
Date 12/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Data Plane Development Kit Overview 3. IFPGA Base Code Design 4. Ethernet Group and Retimer API 5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000
1. About this Document x
1.1. About this Document 1.2. Acronym List
2. Data Plane Development Kit Overview x
2.1. DPDK Intel® FPGA PAC N3000 Software Overview 2.2. DPDK Intel® FPGA PAC N3000 Software Components 2.3. FPGA Scan and Enumeration 2.4. OPAE User Mode Driver 2.5. OPAE User Mode Driver API Summary
2.4. OPAE User Mode Driver x
2.4.1. OPAE FPGA Adapter 2.4.2. OPAE Manager 2.4.3. OPAE Accelerator 2.4.4. OPAE Bridge
2.4.1. OPAE FPGA Adapter x
2.4.1.1. opae_adapter_init() 2.4.1.2. opae_adapter_data_alloc() 2.4.1.3. opae_adapter_enumerate() 2.4.1.4. opae_adapter_destroy()
2.4.2. OPAE Manager x
2.4.2.1. opae_manager_alloc() 2.4.2.2. opae_manager_flash() 2.4.2.3. opae_manager_get_eth_group_region_info() 2.4.2.4. Sensor Information 2.4.2.5. opae_mgr_get_sensor_value_by_name() 2.4.2.6. opae_mgr_get_sensor_value_by_id() 2.4.2.7. opae_mgr_get_sensor_value() 2.4.2.8. opae_manager_networking_ops
2.4.3. OPAE Accelerator x
2.4.3.1. opae_accelerator_alloc() 2.4.3.2. opae_acc_get_uuid() 2.4.3.3. opae_acc_get_region_info() 2.4.3.4. opae_acc_get_info()
2.4.4. OPAE Bridge x
2.4.4.1. opae_bridge_alloc() 2.4.4.2. opae_bridge_reset()
2.5. OPAE User Mode Driver API Summary x
2.5.1. Example Code
3. IFPGA Base Code Design x
3.1. FPGA Management 3.2. Accelerator Access and Control
4. Ethernet Group and Retimer API x
4.1. opae_manager_get_eth_group_nums() 4.2. opae_manager_get_eth_group_info() 4.3. opae_manager_eth_group_write_reg() 4.4. opae_manager_eth_group_read_reg() 4.5. opae_manager_get_eth_group_region_info() 4.6. Data Structures for Retiming 4.7. opae_manager_get_retimer_info() 4.8. opae_manager_get_retimer_status()
1. About this Document
2. Data Plane Development Kit Overview
3. IFPGA Base Code Design
4. Ethernet Group and Retimer API
5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000

2.2. DPDK Intel® FPGA PAC N3000 Software Components

The kernel space uses virtual function I/O (VFIO) to report PCIe* resources to the user space. The VFIO driver advertises direct device access to the user space. Direct access to user space significantly reduces latency, increases bandwidth, and supports direct use of the BareMetal device driver.

Figure 3. DPDK for Intel® FPGA PAC N3000 Software Architecture

The following components make up the DPDK Intel® FPGA PAC N3000 stack. The code path is relative to $RTE_SDK which is the extracted DPDK 19.08 with the patch directory. Refer to the Intel® Acceleration Stack User Guide Intel FPGA Programmable Acceleration Card N3000 for instructions on installing DPDK with the patch.

  • The DPDK PCIe* scan enumerates the PCIe* bus during initialization.
  • The OPAE hardware layer is a common hardware base abstraction layer. This abstraction layer provides hardware function calls and data structures for the FPGA, such as device feature list enumeration.
  • The IFPGA base code specifies the FPGA hardware capability, including FPGA enumeration, and FPGA register access. The code is here: $RTE_SDK/drivers/raw/ifpga/base/
  • The IFPGA bus is new in the DPDK. The DPDK software registers all AFU devices on this bus. The code is here: $RTE_SDK/drivers/bus/ifpga/
  • The Rawdev library defines the raw device type for acceleration devices. For FPGAs the IFPGA Rawdev driver FPGA calls the API that the IFPGA exports to enumerate and discover the management engine (FME) and AFU region. The implementation is here: $RTE_SDK/drivers/raw/ifpga/ifpga_rawdev.c.
  • The afu_device defines a data structure to describe the AFU device, providing access to functions such as memory-mapped I/O (MMIO) read and write.
  • The IPN3KE PMD provides poll mode driver support for the Intel® FPGA PAC N3000. The IPN3KE PMD implements functions that gather the XL710 host side link statistics by making function calls to I40e driver and gathers line side link status and statistics using IFPGA Rawdev driver. This driver is the Ether (Ethernet) driver shown in Figure 3.
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