Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

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ID 683512
Date 12/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Data Plane Development Kit Overview 3. IFPGA Base Code Design 4. Ethernet Group and Retimer API 5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000
1. About this Document x
1.1. About this Document 1.2. Acronym List
2. Data Plane Development Kit Overview x
2.1. DPDK Intel® FPGA PAC N3000 Software Overview 2.2. DPDK Intel® FPGA PAC N3000 Software Components 2.3. FPGA Scan and Enumeration 2.4. OPAE User Mode Driver 2.5. OPAE User Mode Driver API Summary
2.4. OPAE User Mode Driver x
2.4.1. OPAE FPGA Adapter 2.4.2. OPAE Manager 2.4.3. OPAE Accelerator 2.4.4. OPAE Bridge
2.4.1. OPAE FPGA Adapter x
2.4.1.1. opae_adapter_init() 2.4.1.2. opae_adapter_data_alloc() 2.4.1.3. opae_adapter_enumerate() 2.4.1.4. opae_adapter_destroy()
2.4.2. OPAE Manager x
2.4.2.1. opae_manager_alloc() 2.4.2.2. opae_manager_flash() 2.4.2.3. opae_manager_get_eth_group_region_info() 2.4.2.4. Sensor Information 2.4.2.5. opae_mgr_get_sensor_value_by_name() 2.4.2.6. opae_mgr_get_sensor_value_by_id() 2.4.2.7. opae_mgr_get_sensor_value() 2.4.2.8. opae_manager_networking_ops
2.4.3. OPAE Accelerator x
2.4.3.1. opae_accelerator_alloc() 2.4.3.2. opae_acc_get_uuid() 2.4.3.3. opae_acc_get_region_info() 2.4.3.4. opae_acc_get_info()
2.4.4. OPAE Bridge x
2.4.4.1. opae_bridge_alloc() 2.4.4.2. opae_bridge_reset()
2.5. OPAE User Mode Driver API Summary x
2.5.1. Example Code
3. IFPGA Base Code Design x
3.1. FPGA Management 3.2. Accelerator Access and Control
4. Ethernet Group and Retimer API x
4.1. opae_manager_get_eth_group_nums() 4.2. opae_manager_get_eth_group_info() 4.3. opae_manager_eth_group_write_reg() 4.4. opae_manager_eth_group_read_reg() 4.5. opae_manager_get_eth_group_region_info() 4.6. Data Structures for Retiming 4.7. opae_manager_get_retimer_info() 4.8. opae_manager_get_retimer_status()
1. About this Document
2. Data Plane Development Kit Overview
3. IFPGA Base Code Design
4. Ethernet Group and Retimer API
5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000

2.4.3.3. opae_acc_get_region_info()

Prototype:

int opae_acc_get_region_info(struct opae_accelerator *acc, struct opae_acc_info *info);

Arguments:

acc: A pointer to the opae_accelerator struct. 
struct opae_accelerator {
	TAILQ_ENTRY(opae_accelerator) node;
	const char *name;
	int index;
	struct opae_bridge *br;
	struct opae_manager *mgr;
	struct opae_accelerator_ops *ops;
	void *data;
};
info: A pointer to opae_acc_region_info struct: 
struct opae_acc_region_info {
	u32 flags;
	#define ACC_REGION_READ (1 << 0)
	#define ACC_REGION_WRITE (1 << 1)
	#define ACC_REGION_MMIO (1 << 2)
	u32 index;
	u64 phys_addr;
	u64 len;
	u8 *addr;
};

Returns:

Int.

Description:

Get accelerator memory region information that populates the opae_acc_region_info data structure.
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