Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

ID 683512
Date 12/06/2019
Document Table of Contents
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3.2. Accelerator Access and Control

The port hardware consists of an AFU subfeature to provide MMIO region access to the actual AFU.

The ifpga_port_hw data structure stores this information.

struct ifpga_port_hw {
enum ifpga_port_state state;
struct ifpga_feature_list feature_list;
spinlock_t lock; /* protect access to hw */
void *parent; /* pointer to ifpga_hw */
int port_id; /* from HEADER feature */
struct uuid afu_id; /* provied by User AFU feature */
unsigned int disable_count;
u32 capability;
u32 num_umsgs; /* The number of allocated umsgs */
u32 num_uafu_irqs; /* The number of uafu interrupts */
u8 *stp_addr;
u32 stp_size;