Data Plane Development Kit Reference Manual: Intel FPGA Programmable Acceleration Card N3000

Download PDF
ID 683512
Date 12/06/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Data Plane Development Kit Overview 3. IFPGA Base Code Design 4. Ethernet Group and Retimer API 5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000
1. About this Document x
1.1. About this Document 1.2. Acronym List
2. Data Plane Development Kit Overview x
2.1. DPDK Intel® FPGA PAC N3000 Software Overview 2.2. DPDK Intel® FPGA PAC N3000 Software Components 2.3. FPGA Scan and Enumeration 2.4. OPAE User Mode Driver 2.5. OPAE User Mode Driver API Summary
2.4. OPAE User Mode Driver x
2.4.1. OPAE FPGA Adapter 2.4.2. OPAE Manager 2.4.3. OPAE Accelerator 2.4.4. OPAE Bridge
2.4.1. OPAE FPGA Adapter x
2.4.1.1. opae_adapter_init() 2.4.1.2. opae_adapter_data_alloc() 2.4.1.3. opae_adapter_enumerate() 2.4.1.4. opae_adapter_destroy()
2.4.2. OPAE Manager x
2.4.2.1. opae_manager_alloc() 2.4.2.2. opae_manager_flash() 2.4.2.3. opae_manager_get_eth_group_region_info() 2.4.2.4. Sensor Information 2.4.2.5. opae_mgr_get_sensor_value_by_name() 2.4.2.6. opae_mgr_get_sensor_value_by_id() 2.4.2.7. opae_mgr_get_sensor_value() 2.4.2.8. opae_manager_networking_ops
2.4.3. OPAE Accelerator x
2.4.3.1. opae_accelerator_alloc() 2.4.3.2. opae_acc_get_uuid() 2.4.3.3. opae_acc_get_region_info() 2.4.3.4. opae_acc_get_info()
2.4.4. OPAE Bridge x
2.4.4.1. opae_bridge_alloc() 2.4.4.2. opae_bridge_reset()
2.5. OPAE User Mode Driver API Summary x
2.5.1. Example Code
3. IFPGA Base Code Design x
3.1. FPGA Management 3.2. Accelerator Access and Control
4. Ethernet Group and Retimer API x
4.1. opae_manager_get_eth_group_nums() 4.2. opae_manager_get_eth_group_info() 4.3. opae_manager_eth_group_write_reg() 4.4. opae_manager_eth_group_read_reg() 4.5. opae_manager_get_eth_group_region_info() 4.6. Data Structures for Retiming 4.7. opae_manager_get_retimer_info() 4.8. opae_manager_get_retimer_status()
1. About this Document
2. Data Plane Development Kit Overview
3. IFPGA Base Code Design
4. Ethernet Group and Retimer API
5. Revision History for the Data Plane Development Kit Reference Manual: Intel® FPGA PAC N3000

4. Ethernet Group and Retimer API

The Intel® FPGA PAC N3000 defines two Ethernet groups. One group connects to the Intel Ethernet Controller XL710. The other group connects to the retimer. Each Ethernet group supports both the MAC and the PHY components.
Figure 7. Retimer and Line-Side Connectivity for 8x10 GbEThe following figure illustrates the high-level connectivity for retiming when you select 8x10 GbE mode.
The 8x10G mode datapath includes the following components :
  • Two retimers for 10 GbE each connected to 4 channels on the Intel® Arria® 10 FPGA
  • Two Intel Ethernet Controller XL710s for 10 GbE, each connected to 4 channels on the Intel® Arria® 10 FPGA

The following figure illustrates the high-level connectivity for retiming when you select 2x2x25 GbE mode.

Figure 8. Retimer and Line-Side Connectivity for 2x2x25 GbE

The 2x2x25 GbE mode includes the following components for retiming:

  • Two retimers for 25 GbE
  • Two Intel Ethernet Controller XL710 for 2x40 GbE
  • Two ports connected to each retimer
  • Two ports connected to each Intel Ethernet Controller XL710

The following data structures store Ethernet group information: 

struct opae_eth_group_info {
u8 group_id;
u8 speed;
u8 nums_of_phy;
u8 nums_of_mac;
};
Table 8.  opae_eth_group_info Struct Field Definitions
Data Structure Field Name Description
group_id The group index id. The following values are valid for 8x10 GbE mode:
  • 0: The Ethernet group that connects to the retimers
  • 1: The Ethernet group that connects to the XL710.
speed The supported speed of an Ethernet group. For example, on 2x2x25 GbE mode, group 0 supports 25 GbE and group 1 supports 40 GbE.
nums_of_phy The number of PHYs in this group. For 8x10 GbE, there are 8 PHYs and MACs in each group. For 2x2x25 GbE, there are 4 PHYs and 4 MACs in each group.
nums_of_macs The number of MACs in this group. For 8x10 GbE, there are 8 PHYs and MACs in each group. For 2x4x25 GbE, there are 4 PHYs and 4 MACs in each group. 
struct opae_eth_group_region_info {
u8 group_id;
u64 phys_addr;
u64 len;
u8 *addr;
u8 mem_idx;
};
Table 9.  opae_eth_group0_region_info Struct Field Definitions
Data Structure Field Name Description
group_id The group id for this register region.
phys_addr The start physical address of this register region.
len The length of this region.
addr The virtual address of this region.
mem_idx The memory index of the AFU.
The Ethernet group and retimer export the following API functions:
Related Information
Level Two Title