Two variants of Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 are available. Select from the following table to access the corresponding collateral for your variant.
Variant Acceleration Stack Version Part Number Comment
Intel® FPGA PAC N3000 v1.1

BD-NFV-N3000-1 (10 GbE)

BD-NVV-N3000-2 (25 GbE) 

Standard Intel FPGA PAC N3000 N3000
Intel FPGA PAC N3000-N v1.3.1 BD-NVV-N3000-3 Higher thermal capability, NEBS-friendly

Intel® FPGA PAC N3000 Standard Documentation

Documents listed on this page are applicable to the Intel® FPGA PAC N3000-1 and Intel FPGA PAC N3000-2.   

FPGA designers can now develop accelerator functions using hardware description language (HDL) (e.g. Verilog/VHDL). A great way to get started is to install a desired configuration (8x10 GbE, 2x2x25 GbE, or 4x25 GbE) and seamlessly integrate your accelerator function with the software framework and applications on Intel Xeon® CPUs. 

Software developers can make use of the Open Programmable Acceleration Engine (OPAE) software programming layer to develop libraries, frameworks, and applications that call accelerator functions that are implemented in FPGA hardware.

Note: For access to the Intel FPGA Programmable Acceleration Card with N3000 Platform Qualification Guidelines, please contact an Intel representative.

Intel® FPGA PAC N3000-N Documentation

Documents listed on this page are applicable to the Intel® FPGA PAC N3000-N.   

FPGA designers can now develop accelerator functions using the Intel FPGA PAC N3000-N, which has enhanced thermal capability for NEBS-compliant systems. A great way to get started is to install a desired configuration (2x2x25 GbE, or 4x25 GbE) and seamlessly integrate your accelerator function with the software framework and applications on Intel Xeon® CPUs. 

Software developers can make use of the Open Programmable Acceleration Engine (OPAE) software programming layer to develop libraries, frameworks, and applications that call accelerator functions that are implemented in FPGA hardware.

Note: For access to the Intel FPGA Programmable Acceleration Card with N3000-N Platform Qualification Guidelines, please contact an Intel representative.

Training

Suggested Training Class on Persona

Persona

Workload Developers for AFUs (TEM, ISV)

Workload Developers for vRAN

System Integrators (SIs)

Telecommunications Equipment Manufacturers (TEMs)

Original Equipment Manufacturer (OEMs)

Description of Persona

Develop AFUs

Modify vRAN reference design

Package hardware and/or software, and provide to Telco

Develop workload, manage boards (Some will buy servers with Intel FPGA PAC N3000 pre-installed, but some may buy and integrate Intel FPGA PAC 3000 themselves)

Combine and package hardware and firmware into a server

Getting Started with the Intel® FPGA Programmable Acceleration Card N3000 

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Intel® FPGA Programmable Acceleration Card N3000 Security

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Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller

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Building an Accelerator Functional Unit for the Intel® FPGA Programmable Acceleration Card N3000

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Introduction to Intel® FPGA Programmable Acceleration Card N3000

 

 

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vRAN Reference Design Overview and Usage (coming soon)

 

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Open Programmable Acceleration Engine (OPAE) in Depth X X      

FPGA IP Development and Usage

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Checklist for Installation 
(coming soon)

 

 

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Checklist for Board Management
(coming soon)

 

 

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Further Suggested Training Classes

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Data Plane Development Kit (DPDK) Reference Manual: Intel FPGA Programmable Acceleration Card N3000

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AFU: Acceleration Function Unit

OEM: Original Equipment Manufacturer

SIs: System Integrators

TEMs: Telecommunications Equipment Manufacturers

ISV: Independent Software Vendors

vRAN: virtualized Radio Access Network

PAC: Programmable Acceleration Cards