Documents listed on this page are applicable to the Intel® FPGA PAC N3000-1 and Intel FPGA PAC N3000-2.
FPGA designers can now develop accelerator functions using hardware description language (HDL) (e.g. Verilog/VHDL). A great way to get started is to install a desired configuration (8x10 GbE, 2x2x25 GbE, or 4x25 GbE) and seamlessly integrate your accelerator function with the software framework and applications on Intel Xeon® CPUs.
Software developers can make use of the Open Programmable Acceleration Engine (OPAE) software programming layer to develop libraries, frameworks, and applications that call accelerator functions that are implemented in FPGA hardware.
Note: For access to the Intel FPGA Programmable Acceleration Card with N3000 Platform Qualification Guidelines, please contact an Intel representative.