P-Tile Intel® FPGA IPs for PCI Express* IP Cores Release Notes

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ID 683508
Date 10/07/2024
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1. P-Tile IPs for PCI Express IP Core Release Notes
1. P-Tile IPs for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.2.0 1.2. P-Tile IP for PCI Express IP Cores v9.1.2 1.3. P-Tile IP for PCI Express IP Cores v9.1.1 1.4. P-Tile IP for PCI Express IP Cores v9.1.0 1.5. P-Tile IP for PCI Express IP Cores v9.0.3 1.6. P-Tile IP for PCI Express IP Cores v9.0.2 1.7. P-Tile IP for PCI Express IP Cores v9.0.1 1.8. P-Tile IP for PCI Express IP Cores v9.0.0 1.9. P-Tile IP for PCI Express IP Cores v8.3.0 1.10. P-Tile IP for PCI Express IP Cores v8.1.0 1.11. P-Tile IP for PCI Express IP Cores v8.0.0 1.12. P-Tile IP for PCI Express IP Cores v7.0.0 1.13. P-Tile IP for PCI Express IP Cores v6.0.0 1.14. P-Tile IP for PCI Express IP Cores v5.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v4.0.0 1.17. P-Tile IP for PCI Express IP Cores v3.1.0 1.18. P-Tile IP for PCI Express IP Cores v3.0.0 1.19. P-Tile IP for PCI Express IP Cores v2.0.0 1.20. P-Tile IP for PCI Express IP Cores v1.1.0 1.21. P-Tile IP for PCI Express IP Cores v19.3 1.22. P-Tile IP for PCI Express IP Cores v19.2 1.23. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IPs for PCI Express IP Core Release Notes

1.17. P-Tile IP for PCI Express IP Cores v3.1.0

Table 53.  v3.1.0 2020.10.05
Quartus® Prime Version Description Impact
20.3 The BFM for Endpoint mode simulations is not available in this release. It may be available in a future release. Use a third-party BFM for Endpoint mode simulations.
For the P-Tile Avalon Streaming IP, configurations with the Adapter enabled are not available in this release. For the P-Tile Avalon Streaming IP, Gen4 x8 512-bit and Gen4 x4 256-bit configurations are not available in this release.
The Parameter Editor of the P-Tile Avalon Streaming IP indicates support for a 125 MHz application clock frequency in some configurations of the IP. However, this frequency is not supported. If selected, the IP is generated using a 250 MHz application clock. For more details, refer to the following entry in the Intel Knowledge Base page: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/when-using-the-intel--fpga-p-tile-avalon-streaming-ip-for-pci--e.html
Table 54.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 400 MHz 400 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 55.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 56.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H (††) S C T H (†) (††) 350 MHz 350 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A 200 MHz 200 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 200 MHz 200 MHz N/A
Gen3 x16 512-bit S C T H (††) S C T H (†) (††) 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 125 MHz 125 MHz N/A
Note: (†) The design example available in the 20.3 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Quartus® Prime.
Table 57.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H (††) S C T H (†) (††) 400 MHz 400 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A 250 MHz 250 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 250 MHz 250 MHz N/A
Gen3 x16 512-bit S C T H (††) S C T H (†) (††) 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 125 MHz 125 MHz N/A
Note: (†) The design example available in the 20.3 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Quartus® Prime.
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