1.12. P-Tile IP for PCI Express IP Cores v6.0.0
IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Quartus® Prime Version | Description | Impact | |||||||||||
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21.3 | The following signals are added to the Power Management Interface: sys_aux_pwr_det_i apps_ready_entr_l23_i apps_pm_xmt_turnoff_i app_xfer_pending_i |
User application is required to accommodate the new signals for the Power Management Interface. Upgrade to Quartus® Prime Pro Edition v21.3 if Power Management support is required. | |||||||||||
Added support for Gen4 x8/x8 512-bit configuration. | The data bus width increase allows better performance. | ||||||||||||
Added support for Gen3 x16 256-bit configuration. | The new data bus width provides timing closure flexibility. | ||||||||||||
The P-tile Avalon® Streaming and Avalon® Memory-mapped IPs for PCIe do not support parallel PIPE simulations. | There is no plan to add support for parallel PIPE simulations. | ||||||||||||
The Power Management behavior of P-tile IPs for PCIe was updated to align with the behavior of the IPs for other tiles.
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The Power Management behavior is now aligned for IPs for PCIe across P/F/R-tiles. | ||||||||||||
Added support to enable ECRC and LCRC error counters. | Improved error telemetry capabilities by allowing the counting of ECRC and LCRC errors on a PCIe link. |
Configuration | PCIe IP Support | Design Example Support | Timing Support | ||||||
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EP | RP | BP | EP | RP | BP | -1 | -2 | -3 | |
Gen4 x16 512-bit | S C T H | S C T H | S C T H | S C T H | N/A | N/A | 400 MHz | 400 MHz | N/A |
Gen4 x8/x8 256-bit | S C T H | N/A | S C T H | S C T H | N/A | N/A | 450 MHz | 450 MHz | N/A |
Gen4 x4/x4/x4/x4 128-bit | N/A | S C T H | S C T H | N/A | N/A | N/A | 450 MHz | 450 MHz | N/A |
Gen3 x16 512-bit | S C T H | S C T H | S C T H | S C T H | N/A | N/A | 250 MHz | 250 MHz | 250 MHz |
Gen3 x8/x8 256-bit | S C T H | N/A | S C T H | S C T H | N/A | N/A | 250 MHz | 250 MHz | 250 MHz |
Gen3 x4/x4/x4/x4 128-bit | N/A | S C T H | S C T H | N/A | N/A | N/A | 250 MHz | 250 MHz | 250 MHz |
Configuration | PCIe IP Support | Design Example Support | Timing Support | |||||||
---|---|---|---|---|---|---|---|---|---|---|
EP | RP | BP | EP | RP | BP | -1 | -2 | -3 | -4 | |
Gen4 x16 512-bit | S C T H | S C T H | S C T H | S C T H | N/A | N/A | 500 MHz | 500 MHz | 450 MHz | N/A |
Gen4 x8/x8 256-bit | S C T H | N/A | S C T H | S C T H | N/A | N/A | 500 MHz | 500 MHz | 450 MHz | 400 MHz |
Gen4 x4/x4/x4/x4 128-bit | N/A | S C T H | S C T H | N/A | N/A | N/A | 500 MHz | 500 MHz | 450 MHz | 400 MHz |
Gen3 x16 512-bit | S C T H | S C T H | S C T H | S C T H | N/A | N/A | 250 MHz | 250 MHz | 250 MHz | 250 MHz |
Gen3 x8/x8 256-bit | S C T H | N/A | S C T H | S C T H | N/A | N/A | 250 MHz | 250 MHz | 250 MHz | 250 MHz |
Gen3 x4/x4/x4/x4 128-bit | N/A | S C T H | S C T H | N/A | N/A | N/A | 250 MHz | 250 MHz | 250 MHz | 250 MHz |