P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683508
Date 4/11/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.1 1.2. P-Tile IP for PCI Express IP Cores v9.1.0 1.3. P-Tile IP for PCI Express IP Cores v9.0.3 1.4. P-Tile IP for PCI Express IP Cores v9.0.2 1.5. P-Tile IP for PCI Express IP Cores v9.0.1 1.6. P-Tile IP for PCI Express IP Cores v9.0.0 1.7. P-Tile IP for PCI Express IP Cores v8.3.0 1.8. P-Tile IP for PCI Express IP Cores v8.1.0 1.9. P-Tile IP for PCI Express IP Cores v8.0.0 1.10. P-Tile IP for PCI Express IP Cores v7.0.0 1.11. P-Tile IP for PCI Express IP Cores v6.0.0 1.12. P-Tile IP for PCI Express IP Cores v5.0.0 1.13. P-Tile IP for PCI Express IP Cores v4.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v3.1.0 1.16. P-Tile IP for PCI Express IP Cores v3.0.0 1.17. P-Tile IP for PCI Express IP Cores v2.0.0 1.18. P-Tile IP for PCI Express IP Cores v1.1.0 1.19. P-Tile IP for PCI Express IP Cores v19.3 1.20. P-Tile IP for PCI Express IP Cores v19.2 1.21. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.11. P-Tile IP for PCI Express IP Cores v6.0.0

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 31.  v6.0.0 2021.10.04
Quartus® Prime Version Description Impact
21.3

The following signals are added to the Power Management Interface:

sys_aux_pwr_det_i

apps_ready_entr_l23_i

apps_pm_xmt_turnoff_i

app_xfer_pending_i

User application is required to accommodate the new signals for the Power Management Interface. Upgrade to Quartus® Prime Pro Edition v21.3 if Power Management support is required.
Added support for Gen4 x8/x8 512-bit configuration. The data bus width increase allows better performance.
Added support for Gen3 x16 256-bit configuration. The new data bus width provides timing closure flexibility.
The P-tile Avalon® Streaming and Avalon® Memory-mapped IPs for PCIe do not support parallel PIPE simulations. There is no plan to add support for parallel PIPE simulations.

The Power Management behavior of P-tile IPs for PCIe was updated to align with the behavior of the IPs for other tiles.

  EP/UP RP/DP
L2/L3 entry Ok Ok
L2 exit Host to initiate or Cold Reset Cold Reset
L3 exit Cold Reset Cold Reset
The Power Management behavior is now aligned for IPs for PCIe across P/F/R-tiles.
Added support to enable ECRC and LCRC error counters. Improved error telemetry capabilities by allowing the counting of ECRC and LCRC errors on a PCIe link.
Table 32.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 33.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3 -4
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz 400 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz 450 MHz 400 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
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