P-Tile Intel® FPGA IPs for PCI Express* IP Cores Release Notes

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ID 683508
Date 10/07/2024
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1. P-Tile IPs for PCI Express IP Core Release Notes
1. P-Tile IPs for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.2.0 1.2. P-Tile IP for PCI Express IP Cores v9.1.2 1.3. P-Tile IP for PCI Express IP Cores v9.1.1 1.4. P-Tile IP for PCI Express IP Cores v9.1.0 1.5. P-Tile IP for PCI Express IP Cores v9.0.3 1.6. P-Tile IP for PCI Express IP Cores v9.0.2 1.7. P-Tile IP for PCI Express IP Cores v9.0.1 1.8. P-Tile IP for PCI Express IP Cores v9.0.0 1.9. P-Tile IP for PCI Express IP Cores v8.3.0 1.10. P-Tile IP for PCI Express IP Cores v8.1.0 1.11. P-Tile IP for PCI Express IP Cores v8.0.0 1.12. P-Tile IP for PCI Express IP Cores v7.0.0 1.13. P-Tile IP for PCI Express IP Cores v6.0.0 1.14. P-Tile IP for PCI Express IP Cores v5.0.0 1.15. P-Tile IP for PCI Express IP Cores v4.0.0 1.16. P-Tile IP for PCI Express IP Cores v4.0.0 1.17. P-Tile IP for PCI Express IP Cores v3.1.0 1.18. P-Tile IP for PCI Express IP Cores v3.0.0 1.19. P-Tile IP for PCI Express IP Cores v2.0.0 1.20. P-Tile IP for PCI Express IP Cores v1.1.0 1.21. P-Tile IP for PCI Express IP Cores v19.3 1.22. P-Tile IP for PCI Express IP Cores v19.2 1.23. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IPs for PCI Express IP Core Release Notes

1.16. P-Tile IP for PCI Express IP Cores v4.0.0

Table 48.  v4.0.0 2020.12.14
Quartus® Prime Version Description Impact
20.4 Migrating a design using a P-tile Avalon® Streaming or Avalon® Memory-mapped IP from an earlier Quartus® Prime version to the 20.4 version requires an IP upgrade. You must regenerate any design using a P-tile Avalon® Streaming or Avalon® Memory-mapped IP when moving from an earlier Quartus® Prime version to the 20.4 version.
Parameters to enable independent resets for the ports in the bifurcated x8x8 Endpoint mode have been added to the IP Parameter Editor of the P-tile Avalon® Streaming and Avalon® Memory-mapped IPs. Each port in the bifurcated x8x8 Endpoint mode can be reset independently of the other port. Two new reset signals (p0_pld_clrpcs_n, p1_pld_clrpcs_n) are exported to the top-level block symbol when independent resets are enabled. These signals can be assigned to GPIO pins. Contact your local Field Applications Engineer (FAE) for more details.
The parameter to enable the MSI-X capability has been removed from the IP Parameter Editor when the P-tile Avalon® Streaming or Avalon® Memory-mapped IP is in Root Port (RP) mode. The P-tile Avalon® Streaming or Avalon® Memory-mapped IP is not required to support sending MSI-X in RP mode.
The parameter to enable extended tag support has been added to the IP Parameter Editor of the P-tile Avalon Streaming IP. The P-tile Avalon® Streaming IP can support extended tag in this release.
Options to set acceptable Power Management latencies for Endpoints were added to the IP Parameter Editor of the P-tile Avalon® Memory-mapped IP. L0s and L1s acceptable latencies can now be configured in the IP Parameter Editor of the P-tile Avalon® Memory-mapped IP in Endpoint mode.
Options to configure the VSEC parameters in Endpoint mode were added to the IP Parameter Editor of the P-tile Avalon® Memory-mapped IP. VSEC parameters can now be configured in the IP Parameter Editor of the P-tile Avalon® Memory-mapped IP in Endpoint mode.
The parameter to enable VirtIO and SR-IOV capabilities have been removed from the IP Parameter Editor when the P-tile Avalon® Streaming IP is in Root Port (RP) mode. The P-tile Avalon® Streaming IP is not required to support VirtIO or SR-IOV in RP mode.
Options for BAR configuration, Multi-function and SR-IOV support have been removed from the IP Parameter Editor when the P-tile Avalon® Streaming IP is in TLP Bypass mode. The P-tile Avalon® Streaming IP is not required to support these features in TLP Bypass mode.
Options for Multi-function and SR-IOV support support are now visible for Port 1 when the P-tile Avalon® Streaming IP is in a bifurcated mode. Multi-function and SR-IOV support can be enabled for Port 1 when the P-tile Avalon® Streaming IP is in a bifurcated mode.
The IP Parameter Editor response time has been improved for the P-tile Avalon® Streaming IP. The turnaround time after each user input in the IP Parameter Editor is significantly reduced for the P-tile Avalon® Streaming IP in this release.
Table 49.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 400 MHz 400 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 50.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 51.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H (††) S C T H (†) (††) 350 MHz 350 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A 200 MHz 200 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 200 MHz 200 MHz N/A
Gen3 x16 512-bit S C T H (††) S C T H (†) (††) 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 125 MHz 125 MHz N/A
Note: (†) The design example available in the 20.4 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Quartus® Prime.
Table 52.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H (††) S C T H (†) (††) 400 MHz 400 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H (†) N/A 250 MHz 250 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 250 MHz 250 MHz N/A
Gen3 x16 512-bit S C T H (††) S C T H (†) (††) 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H (†) N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A (††) 125 MHz 125 MHz N/A
Note: (†) The design example available in the 20.4 release supports the DMA mode with Data Movers. A design example supporting the Bursting Slave mode may be available in a future release.
Note: (††) This support may be available in a future release of Quartus® Prime.
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