P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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Date 4/11/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.1 1.2. P-Tile IP for PCI Express IP Cores v9.1.0 1.3. P-Tile IP for PCI Express IP Cores v9.0.3 1.4. P-Tile IP for PCI Express IP Cores v9.0.2 1.5. P-Tile IP for PCI Express IP Cores v9.0.1 1.6. P-Tile IP for PCI Express IP Cores v9.0.0 1.7. P-Tile IP for PCI Express IP Cores v8.3.0 1.8. P-Tile IP for PCI Express IP Cores v8.1.0 1.9. P-Tile IP for PCI Express IP Cores v8.0.0 1.10. P-Tile IP for PCI Express IP Cores v7.0.0 1.11. P-Tile IP for PCI Express IP Cores v6.0.0 1.12. P-Tile IP for PCI Express IP Cores v5.0.0 1.13. P-Tile IP for PCI Express IP Cores v4.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v3.1.0 1.16. P-Tile IP for PCI Express IP Cores v3.0.0 1.17. P-Tile IP for PCI Express IP Cores v2.0.0 1.18. P-Tile IP for PCI Express IP Cores v1.1.0 1.19. P-Tile IP for PCI Express IP Cores v19.3 1.20. P-Tile IP for PCI Express IP Cores v19.2 1.21. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.19. P-Tile IP for PCI Express IP Cores v19.3

Table 63.  19.3 September 2019
Description Impact
Initial release of the P-Tile Avalon® -MM IP for PCI Express. This IP supports both Stratix® 10 DX and Agilex™ 7 devices.

Added this new IP component to enable Avalon® -MM support for P-Tile in the Gen3 x16 for Endpoint configuration. The support level is Advance.

Other configurations may be supported in a future release of Quartus® Prime.

The P-Tile Avalon® -MM IP for PCI Express includes internal Read Data Mover and Write Data Mover to support DMA operations. This IP includes Data Mover interfaces to communicate with an external DMA Controller. The Quartus® Prime 19.3 release includes a PCIe DMA design example, which provides a DMA Controller that can interface with the internal Data Movers of the P-Tile Avalon® -MM IP for PCI Express to perform DMA operations. Alternatively, you can build your custom DMA Controller in your application logic.
Added support for the Debug Toolkit for both P-Tile Avalon® -MM and P-Tile Avalon® -ST IPs for PCI Express. The P-Tile Debug Toolkit is a System Console-based tool that provides real-time control, monitoring and debugging of the PCIe links at the Physical Layer.
Clocking topologies with Separate Reference Clock architectures are supported in this release. P-Tile IPs for PCI Express support the Separate Reference Clock with no Spread Spectrum Clocking (SRNS) architecture by default, and the Separate Reference Clock with Independent Spread Spectrum (SRIS) Clocking architecture, which can be enabled from the IP Parameter Editor.
The P-Tile Avalon® -MM IP for PCI Express does not support the Interrupt Interface, Error Interface and Configuration Intercept Interface in this release.

The P-Tile Avalon® -ST IP for PCI Express does support these interfaces.

The P-Tile Avalon® -MM IP for PCI Express may support these interfaces in a future release of Quartus® Prime.

The P-Tile Avalon® -MM IP for PCI Express does not support design example simulation in this release.

The P-Tile Avalon® -ST IP for PCI Express does support design example simulation.

The P-Tile Avalon® -MM IP for PCI Express may support design example simulation in a future release of Quartus® Prime.

You can still simulate the P-Tile Avalon® -MM IP for PCI Express by using a third-party Bus Functional Model (BFM).

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