P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

ID 683508
Date 12/04/2023
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1.4. P-Tile IP for PCI Express IP Cores v9.0.1

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Intel® Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 10.  v9.0.1 2023.04.03
Intel® Quartus® Prime Version Description Impact
23.1 Intel Agilex® 7 FPGAs renamed to Intel Agilex® 7 FPGAs. -
Updated the VCS simulation script for the Intel Agilex® 7 device family. A new command is necessary for proper simulations with the VCS simulator. For additional details, refer to the P-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide.
Table 11.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 450 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 12.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel Agilex® 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3 -4
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x8 256-bit S C T H N/A N/A S C T H N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz 450 MHz 350 MHz
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x8 256-bit S C T H N/A N/A S C T H N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz 250 MHz