P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683508
Date 4/11/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.1 1.2. P-Tile IP for PCI Express IP Cores v9.1.0 1.3. P-Tile IP for PCI Express IP Cores v9.0.3 1.4. P-Tile IP for PCI Express IP Cores v9.0.2 1.5. P-Tile IP for PCI Express IP Cores v9.0.1 1.6. P-Tile IP for PCI Express IP Cores v9.0.0 1.7. P-Tile IP for PCI Express IP Cores v8.3.0 1.8. P-Tile IP for PCI Express IP Cores v8.1.0 1.9. P-Tile IP for PCI Express IP Cores v8.0.0 1.10. P-Tile IP for PCI Express IP Cores v7.0.0 1.11. P-Tile IP for PCI Express IP Cores v6.0.0 1.12. P-Tile IP for PCI Express IP Cores v5.0.0 1.13. P-Tile IP for PCI Express IP Cores v4.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v3.1.0 1.16. P-Tile IP for PCI Express IP Cores v3.0.0 1.17. P-Tile IP for PCI Express IP Cores v2.0.0 1.18. P-Tile IP for PCI Express IP Cores v1.1.0 1.19. P-Tile IP for PCI Express IP Cores v19.3 1.20. P-Tile IP for PCI Express IP Cores v19.2 1.21. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.20. P-Tile IP for PCI Express IP Cores v19.2

Table 64.  19.2 June 2019
Description Impact
Initial release of the P-Tile Avalon® -ST IP for PCI Express. This IP supports both Stratix® 10 DX and Agilex™ 7 devices.

Added this new IP component to enable Avalon® -ST native support for P-Tile in the Gen3 x16/x8 for Endpoint, Gen4 x16/x8 for Endpoint, Gen3 x16/x4 for Root Port and Gen4 x16/x4 for Root Port configurations. The support level is Advance.

Other configurations can be supported through link negotiations.
Support for Single-Root I/O Virtualization (SR-IOV) is available. The P-Tile Avalon® -ST IP for PCI Express supports up to 8 physical functions (PFs) and 2048 virtual functions (VFs) in SR-IOV mode.
Port bifurcation is supported. This IP can support one x16 or two x8 interfaces in Endpoint mode, and four x4 interfaces in Root Port mode.
TLP Bypass mode is supported. This IP supports a TLP Bypass mode for both upstream and downstream ports, thus allowing the implementation of advanced features such as:
  • The upstream port or downstream port of a switch.
  • A custom implementation of a Transaction Layer to meet specific user requirements.
Level Two Title