P-Tile IP for PCI Express* IP Core Release Notes

ID 683508
Date 9/26/2022
Public

1.8. P-Tile IP for PCI Express IP Cores v4.0.0

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel® Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 24.  v4.0.0 2021.03.29
Intel® Quartus® Prime Version Description Impact
21.1 The P-tile Avalon® Memory-mapped IP will not be supported in future releases of Intel® Quartus® Prime. The P-tile Avalon® Memory-mapped IP will not be available in the IP Catalog in future releases of Intel® Quartus® Prime. The replacement IP is the MCDMA-based PCIe Avalon® Memory-mapped IP.
The IP version of the P-tile Avalon® Streaming IP is the same in the 21.1 release and 20.4 release. However, the IP needs to be regenerated when migrating from 20.4 to 21.1. Regenerating the P-tile Avalon® Streaming IP when migrating from 20.4 to 21.1 allows you to take advantage of the 21.1 IP bug fixes and enhancements.

The following note was removed from the P-tile Avalon® Streaming IP for PCI Express* User Guide:

Note: If VirtIO is enabled, the CII is used for VirtIO transport and is not available to the application logic for other purposes.
In 21.1, when VirtIO is enabled, Configuration accesses to the PF/VF VirtIO Capability register range and certain PF/VF PCIe Capability register ranges are not visible to the Configuration Intercept Interface (CII) and can still be issued by the application logic. Refer to the P-tile Avalon® Streaming IP for PCI Express* User Guide for more details.
The design implementation for the VirtIO feature of the P-tile Avalon® Streaming IP has been improved. Resource utilization has been reduced for the P-tile Avalon® Streaming IP when VirtIO is enabled.
The unconstrained clocks issue in the P-tile Avalon® Streaming IP has been fixed. This fix allows you to run a comprehensive timing analysis with all the required clocks constrained on this IP.
Critical timing paths have been optimized for the P-tile Avalon® Streaming IP. The timing closure issue when VirtIO is enabled has also been addressed in this release. Timing margins have been improved for the P-tile Avalon® Streaming IP.
The 2048 VFs issue when VirtIO is enabled in the P-tile Avalon® Streaming IP has been addressed. In 21.1, you can enable all 2048 VFs when VirtIO is enabled.
The P-tile Avalon® Memory-mapped IP does not export the legacy interrupt pin (intx_req_i) when the Enable Legacy Interrupts option is enabled in the IP Parameter Editor. The P-tile Avalon® Memory-mapped IP does not support legacy interrupts in this release. Use MSI or MSI-X instead for interrupts.
Table 25.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 400 MHz 400 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 26.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Agilex™ DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 27.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Intel® Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H N/A S C T H N/A 350 MHz 350 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H N/A 200 MHz 200 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A N/A 200 MHz 200 MHz N/A
Gen3 x16 512-bit S C T H N/A S C T H N/A 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A N/A 125 MHz 125 MHz N/A
Note: The design example available in the 21.1 release supports the DMA mode with Data Movers.
Table 28.  P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCIe Support Matrix for Intel® Agilex™ DevicesEP = Endpoint, RP = Root Port. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP EP RP -1 -2 -3
Gen4 x16 512-bit S C T H N/A S C T H N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 512-bit S C T H N/A S C T H N/A 250 MHz 250 MHz N/A
Gen4 x4/x4/x4/x4 256-bit N/A S C T H N/A N/A 250 MHz 250 MHz N/A
Gen3 x16 512-bit S C T H N/A S C T H N/A 250 MHz 250 MHz N/A
Gen3 x8/x8 512-bit S C T H N/A S C T H N/A 125 MHz 125 MHz N/A
Gen3 x4/x4/x4/x4 256-bit N/A S C T H N/A N/A 125 MHz 125 MHz N/A
Note: The design example available in the 21.1 release supports the DMA mode with Data Movers.

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