P-Tile Intel® FPGA IP for PCI Express* IP Core Release Notes

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Date 4/11/2024
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1. P-Tile IP for PCI Express IP Core Release Notes
1. P-Tile IP for PCI Express IP Core Release Notes x
1.1. P-Tile IP for PCI Express IP Cores v9.1.1 1.2. P-Tile IP for PCI Express IP Cores v9.1.0 1.3. P-Tile IP for PCI Express IP Cores v9.0.3 1.4. P-Tile IP for PCI Express IP Cores v9.0.2 1.5. P-Tile IP for PCI Express IP Cores v9.0.1 1.6. P-Tile IP for PCI Express IP Cores v9.0.0 1.7. P-Tile IP for PCI Express IP Cores v8.3.0 1.8. P-Tile IP for PCI Express IP Cores v8.1.0 1.9. P-Tile IP for PCI Express IP Cores v8.0.0 1.10. P-Tile IP for PCI Express IP Cores v7.0.0 1.11. P-Tile IP for PCI Express IP Cores v6.0.0 1.12. P-Tile IP for PCI Express IP Cores v5.0.0 1.13. P-Tile IP for PCI Express IP Cores v4.0.0 1.14. P-Tile IP for PCI Express IP Cores v4.0.0 1.15. P-Tile IP for PCI Express IP Cores v3.1.0 1.16. P-Tile IP for PCI Express IP Cores v3.0.0 1.17. P-Tile IP for PCI Express IP Cores v2.0.0 1.18. P-Tile IP for PCI Express IP Cores v1.1.0 1.19. P-Tile IP for PCI Express IP Cores v19.3 1.20. P-Tile IP for PCI Express IP Cores v19.2 1.21. P-Tile IPs for PCI Express User Guide Archives
1. P-Tile IP for PCI Express IP Core Release Notes

1.12. P-Tile IP for PCI Express IP Cores v5.0.0

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Quartus® Prime software version to another. A change in:
  • X indicates a major revision of the IP. If you update your Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 34.  v5.0.0 2021.06.25
Quartus® Prime Version Description Impact
21.2 The issue of missing unique tags in module names in generated RTL files for simulation has been fixed in this release. You can run simulations having multiple PCIe IP instances using the generated RTL files for simulation.
Added 450 MHz support for coreclkout_hip for Stratix® 10 DX in Gen4 x8x8 and Gen4 x4x4x4x4 modes. Application logic can have better performance running at 450 MHz.
Added support for Debug Toolkit while in Endpoint mode and using Linux OS.
Using the Debug Toolkit, you can:
  • Report protocol parameters on a per-port basis.
  • Read PHY status information.
  • Perform Eye-plotting for all 16 channels and in x8x8 mode.
Added timing optimization for the Avalon® Streaming PIO design example. Timing margins for the PIO design example for the P-tile Avalon® Streaming IP for PCI Express have been improved.
The Completion Timeout Interface of the Avalon® Streaming PIO design example has been exposed. You can use the Completion Timeout Interface when generating the Avalon® Streaming PIO design example for the P-tile Avalon® Streaming IP for PCI Express.
Added support for independent PERST# in x8x8 mode. You can implement an independent reset for each of the ports in the x8x8 configuration by following the guidelines in Appendix E of the P-tile Avalon® Streaming IP for PCI Express User Guide.
A new checkbox, CvP (Intel VSEC), has been introduced in the IP Parameter Editor to enable CvP support for both the Stratix® 10 DX and Agilex™ 7 device families. When migrating existing CvP designs to Quartus® Prime Pro Edition v21.2, regenerate the IP with the CvP (Intel VSEC) checkbox enabled and recompile the design for the new setting to take effect.
Fixed the issues with Attention Button Pressed and Power Fault Detected Hot-Plug slot events by updating internal IP register settings. No impact on user interfaces. Upgrade to Quartus® Prime Pro Edition v21.2 if Hot Plug support is required.

Enable 10-bit tag support interface option is introduced to expose the p0_10bits_tag_req_en_o [7:0] signal indicating the 10-bit Tag Requester Enable bit of Device Control 2 Register is enabled. However, this feature has the following limitation:

This feature requires the software at the host side to write to the Device Control 2 Register in 1 DWord size. Otherwise, it causes an incorrect value being provided to the user application. This limitation may be resolved in a future release of Quartus® Prime Pro Edition.

This new feature is optional.
There is a limitation on the fix for the issue where the last Physical Function (PF) indicates an incorrect next function number. It does not work correctly when the IP is configured with one Physical Function and multiple Virtual Functions and with Alternative Routing-ID Interpretation (ARI) and Control Services Function Group capabilities enabled. The IP configuration mentioned in the description is not supported in Quartus® Prime Pro Edition v21.2. It may be addressed in a future release.
The IP Parameter Editor window has been tidied up and the IP User Guide has been updated to reflect the changes. No functional impact due to these changes is expected for existing customers.
Table 35.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Stratix® 10 DX DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 400 MHz 400 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 450 MHz 450 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 450 MHz 450 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
Table 36.  P-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support Design Example Support Timing Support
EP RP BP EP RP BP -1 -2 -3
Gen4 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 500 MHz 500 MHz N/A
Gen3 x16 512-bit S C T H S C T H S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x8/x8 256-bit S C T H N/A S C T H S C T H N/A N/A 250 MHz 250 MHz 250 MHz
Gen3 x4/x4/x4/x4 128-bit N/A S C T H S C T H N/A N/A N/A 250 MHz 250 MHz 250 MHz
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