Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: October 07, 2020
Version Found: v20.3
Bug ID: 14012524350
IP: Avalon-ST Stratix 10 Hard IP for PCI Express, pci-express

When using the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express with a 125MHz application clock frequency does the timing analyser report 250MHz being used?

Description

Due to a problem in v20.3 the GUI for the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express, the GUI indicates support for 125MHz application clock frequency in Gen3 capable configurations of the IP. 125MHz application clock frequency is not supported, if selected the IP will be generated using a 250MHz application clock, no warnings, errors or informational messages will be seen.

Workaround/Fix

No workaround for this problem exists in v20.3 of the Intel® Quartus® Prime Pro Edition of software, as 125MHz is not supported.

These incorrect 125MHz options are scheduled to be removed from the next release of the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express IP.