ALTIOBUF IP Core User Guide

ID 683471
Date 1/13/2020
Public

ALTIOBUF Output Buffer

The ALTIOBUF IP core (output buffer mode) uses the output and oe path of the dynamic delay chain, where both share the same IO_CONFIG settings.

Contrary to the input path in the output and oe paths, you can add two optional registers, which are external to the IP core. One is for the output path and the other is for the oe path.

Instead of connecting the input data to the datain port of the ALTIOBUF IP core (output buffer mode), it is connected to the input of the registers that are external to the IP core. The output of the register is then driven to the datain port of the first output delay chain port. In a similar way, the inverted input oe is connected to the oe register that is external to the IP core, which drives the datain port of the first oe delay chain port.

Figure 5.  ALTIOBUF (Output Buffer Mode) Connected with the External Flipflops This figure shows how to connect the output and oe registers to the ALTIOBUF IP core.

Each of the output and oe delay chains are built from two cascaded output delay chains. The first output delay chain’s dataout is connected to the second output delay chain’s datain. Depending on the parameter chosen (use_out_dynamic_delay_chain1 or use_out_dynamic_delay_chain2), one or both of the output delay chains can be dynamic. In this IP core, you can set the delay only for the dynamic delay chains.

The second output delay chain’s dataout is connected to the output buffer’s i input port for the output path and to the output buffer’s oe port for the oe path. Note that the output path and the oe path have their own cascaded delay chains.

Figure 6. Internal Architecture of ALTIOBUF (Output Buffer Mode)This figure shows the internal architecture of the ALTIOBUF IP core.

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