ALTIOBUF IP Core User Guide

ID 683471
Date 1/13/2020
Public

ALTIOBUF Input Buffer

The input buffer IP core uses the input path of the dynamic delay chain.

The datain and datain_b input ports of the ALTIOBUF IP core (input buffer mode) connect to the i and ibar ports (if differential mode is enabled) of the input buffer, respectively. In the input path, the value of the input buffer’s dataout port is passed into the input delay chain. The dataout port of the ALTIOBUF IP core (input buffer mode) is the output of the dataout delay chain.

You must add a register external to the IP core, either a regular DFFE or a DDIO and connect its input to the IP core’s dataout port.

Figure 3. Internal Architecture of ALTIOBUF (Input Buffer Mode)This figure shows the internal architecture of the input buffer in the ALTIOBUF IP core.
Figure 4.  ALTIOBUF (Input Buffer Mode) Connected to the External FlipflopThis figure shows how to connect the external register to the IP core.

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