ALTIOBUF IP Core User Guide

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ID 683471
Date 1/13/2020
Public
Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

Document Revision History for the ALTIOBUF IP Core User Guide

Document Version Intel® Quartus® Prime Version Changes
2020.01.13 19.1 Updated the topic about I/O buffer and dynamic delay integration to clarify that for LVDS interfaces using the ALTLVDS IP core, you enable the dynamic delay in the .qsf file.
2019.11.18 19.1
  • Added table listing the device family support for the ALTIOBUF IP core.
  • Changed document title to ALTIOBUF IP Core User Guide.
  • Names and text rebranded to Intel.
Date Version Changes
June 2017 2017.06.19
  • Added support for Intel® Cyclone® 10 LP devices.
  • Renamed "Quartus II" to "Quartus Prime".
  • Removed topics about the installing and licensing IP cores, IP catalog and parameter editor, customizing and generating IP cores, and upgrading IP cores. These topics are available and updated in Introduction to Intel FPGA IP Cores.
December 2014 2014.12.15 Template update.
2014.06.30 4.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
  • Removed all references to obsolete SOPC Builder tool.
June 2013 3.2
  • Added “Differential Mode Pin Naming Convention”
  • Updated the “Assignments Necessary For Dynamic Delay Chain Usage” to include a link to the ALTDQ_DQS2 Megafunction User Guide.
June 2013 3.1 Updated Table 2–1 on page 2–1 and Table 2–2 on page 2–2 to update the device family support.
February 2012 3.0
  • Updated device support
  • Added references to device handbook for delay chain values
November 2010 2.1
  • Updated to new template
  • Updated ports and parameters
  • Added prototypes and component declarations
December 2008 2.0
  • Added sentence to I/O Buffer and Dynamic Delay Integration
  • Added two last paragraph to Common Applications
  • Added extra note to Table 3–5
  • Remove figures
November 2007 1.0 Initial Release.
Level Two Title