ALTIOBUF IP Core User Guide

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ID 683471
Date 1/13/2020
Public
Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

Verilog HDL Prototype

You can locate the Verilog HDL prototype in the Verilog Design File (.v) altera_mf.v in the < Intel® Quartus® Prime installation directory>\eda\sim_lib directory.

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