ALTIOBUF IP Core User Guide

ID 683471
Date 1/13/2020
Public

ALTIOBUF Signals and Parameters: As Output Buffer

Table 9.   ALTIOBUF (As Output Buffer) Input PortsThis table lists the input ports for the ALTIOBUF IP core (as output buffer).
Name Required Description
datain[] Yes The output buffer input port.

Input port [NUMBER_OF_CHANNELS - 1..0] wide. For differential signals, this port supplies the positive signal input. Inputs are fed to the I/O output buffer element.

io_config_datain No Input port that feeds the datain port of IO_CONFIG for user-driven dynamic delay chain.

Input port used to feed input data to the serial load shift register. The value is a 1-bit wire shared among all I/O instances.

This port is available when the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_clk No Input clock port that feeds the IO_CONFIG for user-driven dynamic delay chain.

Note that the maximum frequency for this clock is 30 MHz.

Input port used as the clock signal of shift register block. The value is a 1-bit wire shared among all I/O instances.

This port is available when the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_clkena[] No Input clock-enable that feeds the ena port of IO_CONFIG for user-driven dynamic delay chain. Input port [NUMBER_OF_CHANNELS - 1..0] wide. Input port used as the clock signal of shift register block.

This port is available when the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_update No Input port that feeds the IO_CONFIG update port for user-driven dynamic delay chain. When asserted, the serial load shift register bits feed the parallel load register. The value is a 1-bit wire shared among all I/O instances.

This port is available when the USE_OUT_DYNAMIC_DELAY_CHAIN1 or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

oe[] No The output-enable source to the tri-state buffer. Input port [NUMBER_OF_CHANNELS - 1..0] wide. When the oe port is asserted, dataout and dataout_b are enabled. When oe is deasserted, both dataout and dataout_b are disabled. This port is used only when the USE_OE parameter value is TRUE. If omitted, the default is VCC.
seriesterminationcontrol[] No Receives the current state of the pull up and pull down Rs control buses from a termination logic block. Input port [WIDTH_STC * NUMBER_OF_CHANNELS - 1..0] wide.

Port is available only when the USE_TERMINATION_CONTROL parameter value is TRUE.

seriesterminationcontrol_b No Receives the current state of the pull up and pull down Rs control buses from a termination logic block. Input port [WIDTH_STC * NUMBER_OF_CHANNELS - 1..0] wide.

Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.

parallelterminationcontrol[] No Receives the current state of the pull up and pull down Rt control buses from a termination logic block. Input port [WIDTH_PTC * NUMBER_OF_CHANNELS - 1..0] wide. The port is available for Stratix® III device families only. Supported in Stratix® series only.

Port is available only when the USE_TERMINATION_CONTROL parameter value is TRUE.

parallelterminationcontrol_b No Receives the current state of the pull up and pull down Rt control buses from a termination logic block. Input port [WIDTH_PTC * NUMBER_OF_CHANNELS - 1..0] wide. Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE. The port is available for Stratix® III device families only. Supported in Stratix® series only.

Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.

Table 10.   ALTIOBUF (As Output Buffer) Output PortsThis table lists the output ports for the ALTIOBUF IP core (as output buffer).
Name Required Description
dataout[] Yes Output buffer output port. Output port [NUMBER_OF_CHANNELS - 1..0] wide. The I/O output buffer element output.
dataout_b[] No Differential output buffer-negative output. Output port [NUMBER_OF_CHANNELS - 1..0] wide. The I/O output buffer negative output.

Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.

Table 11.   ALTIOBUF (As Output Buffer) ParameterThis table lists the parameters for the ALTIOBUF IP core (as output buffer).
Name Required Type Description
ENABLE_BUS_HOLD No String Specifies whether the bus hold circuitry is enabled. Values are TRUE and FALSE. When set to TRUE, bus hold circuitry is enabled, and the previous value, instead of high impedance, is assigned to the output port when there is no valid input. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

USE_DIFFERENTIAL_MODE No String Specifies whether the output buffer mode is differential. Values are TRUE and FALSE. When set to TRUE, both the dataout and dataout_b ports are used. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

OPEN_DRAIN_OUTPUT No String Open drain mode. Values are TRUE and FALSE. If omitted, the default is FALSE.
Note: Currently, OPEN_DRAIN_OUTPUT and USE_DIFFERENTIAL_MODE cannot be used simultaneously.
USE_TERMINATION_CONTROL No String Specifies series termination control and parallel termination control. Values are TRUE and FALSE. If omitted, the default is FALSE. When this parameter is used for Arria® II GX devices and the Cyclone® series, only series termination control is available. Stratix® series support both.
USE_OUT_DYNAMIC_DELAY_CHAIN1 No String Specifies whether the output buffer incorporates a user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and the first output delay cell. Additional input ports are io_config_clk, io_config_clkena, io_config_update, and io_config_datain. Values are TRUE and FALSE. If omitted, the default is FALSE.
USE_OUT_DYNAMIC_DELAY_CHAIN2 No String Specifies whether the output buffer incorporates a user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and the second output delay cell. Additional input ports are io_config_clk, io_config_clkena, io_config_update, and io_config_datain. Values are TRUE and FALSE. If omitted, the default is FALSE.
NUMBER_OF_CHANNELS Yes Integer Specifies the number of I/O buffers that must be instantiated. Value must be greater than or equal to 1. A value of 1 indicates that the buffer is a 1-bit port and accommodates wires. A value greater than 1 indicates that the port can be connected to a bus of width NUMBER_OF_CHANNELS.
WIDTH_STC No Integer Specifies the width setting for the series termination control bus.
WIDTH_PTC No Integer Specifies the width setting for the parallel termination control bus.
USE_OE No String Specifies whether the oe port is used.
LEFT_SHIFT_SERIES_TERMINATION_CONTROL No String Values are True and False. If omitted, the default is False. Available for all supported devices except Cyclone® series device family.
PSEUDO_DIFFERENTIAL_MODE No String Specifies the pseudo differential mode. Values are True and False. If omitted, the default is False. Available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.

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