ALTIOBUF IP Core User Guide

ID 683471
Date 1/13/2020
Public

ALTIOBUF Parameters

This table lists the options ALTIOBUF IP core parameters.
Table 2.   ALTIOBUF IP Core Parameters: General Tab
Parameter Description
Currently selected device family: Specify the device family you want to use.
How do you want to configure this module? Specify whether it is an input buffer, output buffer, or bidirectional buffer.
What is the number of buffers to be instantiated? Specify the number of buffers to be used. This defines the size of the buffer.
Use bus hold circuitry If enabled, the bus-hold circuitry can weakly hold the signal on an I/O pin at its last-driven state. Available in input buffer, output buffer, or bidirectional buffer.
Use differential mode If enabled, datain/datain_b is used for input buffers, both dataout/dataout_b are used for output buffers, and both dataio/dataio_b are used for bidirectional buffers.
Use open drain output If enabled, the open drain output enables the device to provide system-level control signals (for example, interrupt and write-enable signals) that can be asserted by multiple devices in your system. This option is only available for output buffers and bidirectional buffers.
Use output enable port(s) If enabled, there is a port used to control when the output is enabled. This option is only available for output buffers and bidirectional buffers.
Use dynamic termination control(s) If enabled, this port receives the command to select either Rs code (when input value = low) or Rt code (when input value = high) from the core. Only enable Rt when the bi-directional I/O is receiving input. Otherwise, it needs to be disabled so that the output performance and power dissipation is optimal. This option is available only for input and bidirectional buffers.

An error is issued if parallel termination (Rt) is on and dynamic termination control is not connected on a bidir pin. An error is issued if parallel termination (Rt) is off and dynamic termination control is connected on an input or bidirectional pin.

Note that two I/Os in the same dynamic termination control group needs to have the same dynamic termination control signal. If the I/Os have separate dynamic termination control signals, the Intel® Quartus® Prime software produces a fitting error. A dynamic termination control group is a group of pins that share the same physical dynamic termination control signal on the chip.

This option is not available in Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

Use series and parallel termination controls If enabled, this allows the series and parallel termination control ports to be used. These ports can then be connected to termination logic blocks to receive the Rs or Rt code from the termination logic blocks.

This option is only available for output buffers and bidirectional buffers. The series and parallel termination control ports are 14-bit wide for series or parallel termination.

For Cyclone® III, Cyclone® IV, Intel® Cyclone® 10 LP, and Cyclone® V devices, this option is available for output buffers and bidirectional buffers, but not for input buffers. Only series termination is available. The series termination control ports are 16-bit wide. The width of these ports increases depending on the amount of buffers instantiated.

Use left shift series termination control If enabled, you can use the left shift series termination control to get the calibrated OCT Rs with half of the impedance value of the external reference resistors connected to RUP and RDN pins. This option is useful in applications which required both 25-Ω and 50-Ω calibrated OCT Rs at the same Vccio. For more information, refer to I/O features chapter of the respective device handbooks.
Table 3.   ALTIOBUF Parameters: Dynamic Delay Chains Tab
Parameter Description
Enable input buffer dynamic delay chain If enabled, the input or bidirectional buffer incorporates the user-driven dynamic delay chain in the IP core; that is, the IO_CONFIG and the input delay cell. Additional input ports are enabled: io_config_clk, io_config_clkena, io_config_update, and io_config_datain.

This option is not available for Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

Enable output buffer dynamic delay chain 1 If enabled, the output or bidirectional buffer incorporates the user-driven dynamic delay chain in the IP core; that is, the IO_CONFIG and the first output delay cell. Additional input ports are enabled: io_config_clk, io_config_clkena, io_config_update, and io_config_datain.

This option is not available for Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

Enable output buffer dynamic delay chain 2 If enabled, the output buffer or bidirectional buffer incorporates a user-driven dynamic delay chain in the IP core; that is, the IO_CONFIG and the second output delay cell. Additional input ports are enabled: io_config_clk, io_config_clkena, io_config_update, and io_config_datain.

This option is not available for Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

Create a ‘clkena’ port If enabled, there is a port used to control when the configuration clock is enabled. This option is not available for Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

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