ALTIOBUF IP Core User Guide

ID 683471
Date 1/13/2020

ALTIOBUF Bidirectional Buffer

The bidirectional buffer essentially combines the input buffer and the output buffer, incorporating the input path, output path, and oe path.

By combining the input and output buffers, the output path and oe path are placed before the buffer and the input path is placed after the buffer.

Figure 7. Internal Architecture of ALTIOBUF (Bidirectional Buffer Mode)

By following these specifications, only the input path needs a register external to the IP core. The output and oe registers that are added externally to the IP core are optional.

Figure 8.  ALTIOBUF (Bidirectional Buffer Mode) Connected with External FlipflopsThis figure shows an example of the ALTIOBUF IP core (bidirectional buffer mode) when output, oe, and input path registers are used that are external to the IP core.

The external register placement is similar to the input/output buffers, where the output and oe registers drive the datain and oe ports of the ALTIOBUF IP core (bidirectional buffer mode) and the dataout port drives the input register.

  • The dynamic termination control path also contains output delay chain 1 and output delay chain 2, which are not accessible through the ALTIOBUF IP core (bidirectional buffer mode). When both the oe and dynamic termination control are used, the two signals (oe and dynamic termination control) can be out of synchronization.
  • It is not recommended to switch these two signals simultaneously.

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