3.1. Software Description
All the IPs in the UHD HDMI 2.0 Video Format Converison Design Example can process frames of data without any further intervention once they are setup correctly. However, the design requires external high-level control to setup the IPs to begin with and when any changes occur in the system, e.g. HDMI RX or TX hot-plug events, or user push button activity. In the design, a Nios II processor running bespoke control software provides the high-level control.
At startup the software:
- Sets the DDR4 ref clock to 150 MHz to allow for 1200 MHz DDR speed, then resets EMIF to recalibrate on the new reference clock.
- Sets up the TI TDP158 HDMI 2.0 redriver and TI TMDS181C retimer
- Initializes the HDMI RX and TX interfaces
- Initializes the processing pipeline IPs
After initialization, the software enters a continuous while loop, checking for and reacting to the following events.
Changes to the Scaling Mode
The design supports three basic scaling modes; passthrough, upscale, and downscale. In passthrough mode the input video is not scaled; in upscale mode the input video is upscaled, and in downscale mode the input video is downscaled. Four blocks determine the presentation of the final output in each mode in the processing pipeline: the clipper, the downscaler, the upscaler, and the mixer. The software controls the settings of each block depending on the current input resolution, output resolution, and the scaling mode that you select. In most cases, the clipper passes the input through unaltered, and the mixer background size is the same size as the final, scaled version of the input video. However, if the input video resolution is greater than the output size, the design cannot apply an upscale to the input video without first clipping it. And if the input resolution is less than the output, the design cannot apply a downscale without using a mixer background layer that is larger than the input video layer, which adds black bars around the output video.| Mode | Input size > output size | Input size = output size | Input size < output size |
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| Passthrough |
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| Upscale |
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| Downscale |
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Changes at the HDMI Input
On each run through the loop the software polls the status of the clocked video input (CVI), looking for changes in the stability of the input video stream. The design considers the video stable if the CVI reports that the clocked video is successfully locked, and if the input resolution and color space has not changed since the previous run through the loop.
If the design previously considers the input stable, but it loses the lock or the properties of the video stream change, the software stops the CVI sending video through the pipeline, and sets the mixer to stop displaying the input video layer. Then the output remains active (showing a black screen and the Intel icon) during any RX hot-plug events or resolution changes.
If the input was not previously stable but is now stable, the design configures the pipeline to best display the new input resolution and color space, restarts the output from the CVI, and sets the mixer to display the input video layer once again. The re-enabling of the mixer layer is not immediate as the Frame Buffer may still be repeating old frames from a previous input, which the design must clear before you can re-enable the display to avoid glitching. The frame buffer keeps a count of the number of frames the design reads from the DDR4 memory, and the Nios II processor reads this count. The software samples this count when the input becomes stable, and re-enables the Mixer layer when the count increases by four frames. More than sufficient to ensure the design flushes any old frames from the buffer.
HDMI TX Hot-plug Events
The software polls the HDMI TX IP on each run through the loop to check for hot-plug events. When the design detects a TX hot plug, the design reads the EDID for the new display to determine which resolutions and color spaces it supports. If you set the DIP switches to a mode that the new display cannot support, the software falls back to a less demanding display mode. It then configures the pipeline, HDMI TX IP and the Si5338 part that generates the TX vid_clk for the new output mode. The design does not display the mixer layer for the input video while it edits the settings for the pipeline. The design does not re-enable the display until four frames with the new settings pass through the frame buffer.
Changes to User DIP Switch Settings
The positions of DIP switches 2 to 6 control the output format (resolution, frame rate, color space and bits per color) that drives through the HDMI TX. When the design detects any changes on these DIP switches, the software runs through a sequence that is similar to a TX hot-plug. The only difference in this case is that the TX EDID does not need to be queried as this has not changed.