AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

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ID 683465
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the UHD HDMI 2.0 Video Format Conversion Design Example 2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started 3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description 4. Considering Design Security 5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History A. HDMI RX Interface Register Map B. HDMI TX Interface Register Map
1. About the UHD HDMI 2.0 Video Format Conversion Design Example x
1.1. UHD HDMI 2.0 Video Format Conversion Design Example Features
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started x
2.1. Hardware and Software Requirements for the UHD HDMI 2.0 Video Format Conversion Design Example 2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example 2.3. Setting up the Intel® Arria® 10 FPGA development board 2.4. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example 2.5. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example with the Nios II Software Tools for Eclipse 2.6. Running the UHD HDMI 2.0 Video Format Conversion Design Example on the Hardware
2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example x
2.2.1. Installation Files for the UHD HDMI 2.0 Video Format Conversion Design Example
2.3. Setting up the Intel® Arria® 10 FPGA development board x
2.3.1. Board Status Lights, DIP Switches, and Pushbuttons
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description x
3.1. Software Description
1. About the UHD HDMI 2.0 Video Format Conversion Design Example
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description
4. Considering Design Security
5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History
A. HDMI RX Interface Register Map
B. HDMI TX Interface Register Map

2.5. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example with the Nios II Software Tools for Eclipse

The design includes a shell script file (/software/script/script_build_sw.sh) to help you quickly build the Nios II software code for the design. The script allows you to quickly generate the programming files for the Nios II processor. However, it does not set up a workspace that allows interactive debugging of the software code.
You can follow the steps to compile the design software, which allows you to debug the design. Or you can run the Intel-provided script. To run the script:
  1. In Windows Explorer, navigate to the <install_dir>/software/script directory with all of the necessary software files.
  2. In a terminal from the script directory run the shell script build_sw.sh, which generates an executable vip_control.elf in the vip_control directory.
    Note: this scripts overwrites files in the vip_control directory. Edit any source files in the vip_control_src directory only.

STEPS:

  1. In the installed project directory, create a new folder and name it workspace.
  2. In the Intel Quartus Prime software, click Tools > Nios II Software Build Tools for Eclipse > .
    1. In the Workspace Launcher window, select the workspace.
    2. Click OK.
  3. In the Nios II – Eclipse window, click File > New > Nios II Application and BSP from Template.
    The Nios II Application and BSP from Template dialog box appears.
    1. In the SOPC Information File box, select the udx10_hdmi/udx10_hdmi.sopcinfo file.
      The Nios II SBT for Eclipse fills in the CPU name with the processor name from the .sopcinfo file..
    2. In the Project name box, type vip_control.
    3. Select Blank Project from the Templates list and then click Next.
    4. Select Create a new BSP project based on the application project template with the project name vip_control_bsp and turn on Use default location.
    5. Click Finish to create the application and the BSP based on the .sopcinfo file.
      After the BSP generates, the vip_control and vip_control_bsp projects appear in the Project Explorer tab.
  4. In Windows Explorer, copy the contents of the software/vip_control_src directory to the software/vip_control directory.
  5. In Project Explorer tab of the Nios II - Eclipse window, right click on the vip_control_bsp folder and select Nios II > BSP Editior…
    1. Select none from the drop-down menu for sys_clk_timer
    2. Select cpu_timer from the drop-down menu for timestamp_timer
    3. Turn on enable_small_c_library
    4. Click Generate.
    5. When generation completes, click Exit
  6. Select Project > Build All to generate the file vip_control.elf in the software/vip_control directory.
  7. Build the mem_init file for the Intel Quartus Prime compilation:
    1. Right click on vip_control in the Project Explorer window.
    2. Select Make Targets > Build…
    3. Select mem_init_generate and click Build.
      The Intel Quartus Prime software generates the udx10_hdmi_onchip_memory2_0_onchip_memory2_0.hex file in the software/vip_control/mem_init directory
  8. With the design already running on a connected board, run the vip_control.elf programming file created by the Eclipse build
    1. Right click on the vip_control folder in the Project Explorer tab of the Nios II – Eclipse window.
    2. Select Run As > Nios II Hardware.
      If you have a Nios II terminal window already open, close it before trying to download new software.
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