AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

ID 683465
Date 4/15/2021
Public
Document Table of Contents

A. HDMI RX Interface Register Map

The HDMI RX interface component presents two Avalon memory-mapped agent interfaces for connection to the Nios II processor.

The edid_slave interface provides a mechanism to connect to the EDID Avalon memory-mapped agent interface on the HDMI protocol IP, which sits outside the Platform Designer system. The register map for this interface is in the HDMI IP User Guide.

The info_slave interface is primarily allows the Nios II to access the HDMI RX AVI Infoframe data from the HDMI RX IP, but which also provides access to some signals associated to configuring the transceivers that otherwise needs to be accessed via PIOs.
Table 6.  HDMI RX Register Map

Address

(byte)

Address (Word) Permission Name Description
0 0 Read only HDMI RX GCP HDMI General Control Packet currently output by the HDMI RX IP
1 – 13 4 – 52 Read only HDMI RX AVI Infoframe HDMI AVI Infoframe currently output by the HDMI RX IP. The AVI Infoframe is output by the HDMI RX as a 112 bit signal. Bits[7:0] are the checksum and are not exposed through the register map. Registers 1 through 13 each provide access to one byte of the remaining 104 bits of this interface, with bits[15:8] in register 1 and bits [103:96] in register 13
14 56 Read only TMDS Bit clock ratio Bit[0] of this register provides the current value of TMDS Bit clock ratio output by the HDMI RX IP. This value indicates if TMDS Bit Rate is greater than 3.4 Gbps.
15 60 Read only Unused Unused
16 64 Read only PMA Busy Bit[0] is 1 if the transceiver reconfig is busy
17 68 Writeable RX reset transceiver The value in bit[0] is driven onto the transceiver reset for the HDMI RX
18 72 Writeable RX transceiver reconfig enable Writing 1 to bit[0] of this register enables reconfiguration of the RX transceiver settings
19 76 Writeable RX transceiver reconfig channel Sets which RX transceiver channel new settings should be applied to

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