AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

ID 683465
Date 4/15/2021
Document Table of Contents

3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description

A Platform Designer system, udx10_hdmi.qsys, contains the video pipeline IP and the Nios® II processor components. The top-level Verilog HDL file (top.v) connects the Platform Designer system to the HDMI RX and TX. The design comprises a single video processing path between the HDMI input and the HDMI output.
Figure 2. Block Diagram

The diagram shows the incoming video from the HDMI source on the left. The design processes the video through the video pipeline from left to right before passing the video out to the HDMI sink on the right.. The diagram does not show some of the generic peripherals connected to the Nios II processor or the Avalon memory-mapped interface between the Nios II processor and the other components of the system.


The Bitec HDMI FMC card provides a buffer for the HDMI 2.0 signal from the HDMI source. The combination of HDMI RX PHY and HDMI RX IP decode the incoming signal to create a video stream. The HDMI RX PHY contains the transceivers to deserialize the incoming data and the HDMI RX IP decodes the HDMI protocol. The combined HDMI RX IP processes the incoming HDMI signal without any software intervention. The resulting video signal from the HDMI RX IP is a clocked video streaming format. The design configures the HDMI RX for 10-bit output.

HDMI RX Interface

The clocked video streaming data format output by the HDMI RX IP is compatible with the clocked video data format expected by the Clocked Video Input IP, which is next in the processing chain. However, the wire level interfaces have subtle differences that prevent a direct connection between the two blocks. The design-specific custom HDMI RX interface aligns the signals output by the HDMI and received by the Clocked Video Input IP.

The HDMI RX interface modifes the wire signaling standard and alters the order of the color planes within each pixel. This is required to translate between the HDMI standard color ordering and that used by the Intel video pipeline IP. The color swap is controlled by the HDMI RX AVI Infoframe data, which is an additional input to this block.

This component serves as a convenient register map based interface to access the HDMR RX AVI Infoframe data, program the RX EDID, and provide some of the transceiver reconfiguration settings. For more information on the register map, refer to HDMI RX Interface Register Map.

Clocked Video Input

The clocked video input processes the clocked video interface signal from the HDMI RX IP and converts it to Intel proprietary Avalon streaming Video format. This format strips all horizontal and vertical blanking information from the video, leaving only active picture data. The design packetizes the data as one packet per video frame and adds additional metadata packets (referred to as control packets) that describe the resolution of each video frame. For a full description of Avalon streaming video interface refer to the Avalon Interface Specification. The Avalon streaming video stream through the processing pipe is two pixels in parallel, with three symbols per pixel. The clocked video input provides clock crossing for the conversion from the variable rate clocked video signal from the HDMI RX IP to the fixed clock rate (300 MHz) for the video IP pipeline.

Stream Cleaner

The stream cleaner ensures that the Avalon streaming video signal passing to the processing pipeline is error free. Hot-plugging of the HDMI source can cause the design to present incomplete frames of data to the clocked video input IP, which generates errors in the resulting Avalon-ST Video stream where the size of the packets containing the video data for each frame do not match the size reported by the associated control packets. The stream cleaner detects these conditions and adds additional data (grey pixels) to the end of the offending video packets to complete the frame and match the specification in the control packet.

Chroma Resampler (Input)

The video data received at the input via HDMI may be 4:4:4, 4:2:2 or 4:2:0 chroma sampled. The input chroma resampler takes the incoming video in whatever format it arrives and converts it to 4:4:4. To provide higher visual quality, the chroma resampler use the most computationally expensive filtered algorithm. The Nios II processor reads the current chroma sampling format from the HDMI RX via its Avalon memory-mapped agent interface, and communicates this data to the chroma resampler via its Avalon memory-mapped agent interface.

Color Space Converter (Input)

The video data received at the input via HDMI may use either the RGB or YCbCr color space. The input color space converter takes the incoming video in whatever format it arrives and converts it to RGB in all cases, for the Mixer IP later in the pipeline. The Nios II processor reads the current color space from the HDMI RX via its Avalon memory-mapped agent interface and loads the correct conversion coefficients to the color space converter via its Avalon memory-mapped agent interface.


The deinterlacer creates progressive video content from interlaced streams received at the input. It propagates progressive data unaltered. The deinterlacer can only run up to 150 MHz, so the design includes clock crossing and data width conversion (2->4 pixels per clock at the input, 4->2 pixels per clock at the output) components on either side of the deinterlacer. The deinterlacer is limited to the standard highest resolution for interlaced data of 1080i60.


The clipper selects an active area from the incoming video stream and discards the remainder. The software control running on the Nios II processor defines the region to select. The region depends on the resolution of the data received at the HDMI source and the output resolution and scaling mode you select via the DIP switches and push buttons on the board. This design communicates this region to the Clipper via its Avalon memory-mapped agent interface.


The design applies scaling to the incoming video data according the input resolution and the output resolution that you request. You may also select one of three scaling modes (upscale, downscale and passthrough) that affect how the video scales and displays. Two separate Scaler IPs provide the scaling functionality: one which implements any required downscaling, and another which upscales. The design requires two scalers for the following reasons.

When the scaler implements a downscale it does not produce valid data on every clock cycle at its output. For example, if implementing a 2x downscale ratio, the valid signal at the output is high every other clock cycle while each even numbered input line is received, and then low for the entirety of the odd numbered input lines. This bursting behavior is fundamental to the process of reducing the data rate at the output, but is incompatible with the downstream Mixer IP, which generally expects a more consistent data rate to avoid underflow at the output. The Frame Buffer must sit between any downscale and the Mixer, as going through the Frame Buffer allows the Mixer to read the data at the rate it requires.

When the scaler implements an upscale it produces valid data on every clock cycle for the following Mixer. However, it may not accept new input data on every clock cycle. Taking a 2x upscale as an example, on the even numbered output lines it accepts a new beat of data every other clock cycle, then accepts no new input data on the odd numbered output lines. The upstream Clipper produces data at an entirely different rate if it is applying a significant clip (e.g. during a zoom-in). For this reason, you must generally separate a Clipper and upscale by a frame buffer, requiring the scaler to sit after the frame buffer in the pipeline. The Scaler must sit before the Frame Buffer for downscales, so we must use two separate scalers either side of the Frame Buffer and use one for upscale and the other for downscale.

Using two Scalers reduces the maximum DDR4 bandwidth required by the Frame Buffer. Downscales are always applied before the Frame Buffer, minimizing the data rate on the write side. Upscales are applied after the Frame Buffer, which minimizes the data rate on the read side.

Each Scaler obtains the required input resolution from the control packets in the incoming video stream, while the output resolution for each Scaler is set by the Nios II processor via the Avalon memory-mapped agent interface. At least one of the scalers is configured for passthrough in each scaling mode. So if the design is upscaling video content then the downscaler pass video through unaltered, and if the design is downscaling the upscaler passes video through unaltered.

Frame Buffer

The frame buffer uses the DDR4 memory to perform triple buffering that allows the video and image processing pipeline to perform frame rate conversion between the incoming and outgoing frame rates. The design can accept any input frame rate assuming the total pixel rate does not exceed 1 giga pixels per second. The output frame rate is set to either 30 or 60 fps by the Nios II software, according to the output mode you select. The output frame rate is actually a function of the Clocked Video Output settings and the output video pixel clock and is not set in the Frame Buffer. The backpressure applied by the Clocked Video Output to rest of the pipeline determines the rate at which the read side of the Frame Buffer pulls video frames from the DDR4 memory.


The mixer generates a fixed size black background image that the Nios II processor first input connects to the upscaler to allow the design to show the output from the current video pipeline. The second input connects to the icon generator block. The design only enables the mixer's first input when it detects active, stable video at the clocked video input. The design maintains a stable output image at the output while hot-plugging at the input. The design alpha-blends the second input to the mixer, connected to the icon generator, over both the background and video pipeline images with 50% transparency.

Color Space Converter (Output)

The output color space converter transforms the input RGB video data to either RGB or YCbCr color space based on the runtime setting from software.

Chroma Resampler (Output)

The output chroma resampler converts the format from 4:4:4 to one of 4:4:4, 4:2:2 and 4:2:0 and is set by the software. The output chroma resampler also uses filtered algorithm to achieve high-quality video.

Clocked Video Output

The clocked video output converts the Avalon streaming video stream to the clocked video format. The clocked video output adds horizontal and vertical blanking and synchronization timing information to the video. The Nios II processor programs the relevant settings in the clocked video output depending on the output resolution and frame rate you request. The clocked video output converts the clock, crossing from the fixed 300 MHz pipeline clock to the variable rate of the clocked video.

HDMI TX Interface

The HDMI TX interface accepts data formatted as clocked video. Subtle differences in the wire signaling and declaration of the conduit interfaces in Platform Designer prevent the design connecting the Clocked Video Output directly to the HDMI TX IP. The design-specific custom HDMI TX interface provides the simple conversion required between the Clocked Video Output and the HDMI TX IP. It also swaps the ordering of the color planes in each pixel to account for the different color formatting standards used by Avalon streaming video and HDMI, and provides a register map to access some of the transceiver reconfiguration and HDMI TX AVI Infoframe settings. For more information on the register map, refer to HDMI TX Interface Register Map.


THE HDMI TX IP and PHY convert the video stream from clocked video to a compliant HDMI stream. The HDMI TX IP handles the HDMI protocol and encodes the valid HDMI data. The HDMI TX PHY contains the transceivers and creates the high-speed serial output.

Nios II Processor and Peripherals

The Platform Designer system contains a Nios II Processor that manages the HDMI RX and TX IPs and the runtime settings for the processing pipeline. The Nios II processor connects to serval other basic peripherals:
  • An on-chip memory to store the program and its data.
  • A JTAG UART to display software printf output (via a Nios II terminal)
  • A system timer to generate millisecond level delays at various points in the software, as required by the HDMI specification of minimum event durations.
  • LEDs to display system status.
  • Push-button switches to allow switching between scaling modes and to enable and disable display of the Intel icon
  • DIP switches to allow switching of the output format and to enable and disable the printing of messages to a Nios II terminal
  • Hot-plug events on both the HDMI source and sink fire interrupts that trigger the Nios II Processor to configure the HDMI TX and pipeline correctly. The main loop in the software code also monitors the values on the push-buttons and DIP switches and alters the pipeline setup accordingly.

I²C controllers

  • The design contains two I²C controllers to edit the settings of four other components on the Arria 10 GX FPGA Development Kit and Bitec HDMI 2.0 daughter card:
    • Si5338 I²C. The Arria 10 GX FPGA Development Kit includes two Si5338 clock generators on which both connect to the same I²C bus. The first generates the reference clock for the DDR4 EMIF. By default, this clock is set to 100 MHz for use with 1066 MHz DDR4, but for this design runs the DDR4 at 1200 MHz which requires a reference clock of 150 MHz. At startup, the Nios II processor, via the I²C controller peripheral, changes the settings in the register map of the first Si5338 to increase the speed of the DDR4 reference clock to 150 MHz. The second Si5338 clock generator generates the vid_clk for the clocked video interface between the pipeline and the HDMI TX IP. The Nios II processor adjusts the speed of this clock at runtime for each different output resolution and frame rate supported by the design.
    • TI I²C .The Bitec HDMI 2.0 FMC daughter card uses the TI TDP158 HDMI 2.0 redriver and TI TMDS181C retimer. At startup the Nios II processor edits the default settings of these component to meet the requirements of the design.

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